Semiconductor hybrid component

• US 5,726,500 A
• Filed: 12/07/1995
• Issued: 03/10/1998
• Est. Priority Date: 04/08/1994
• Status: Expired due to Fees

• Current Assignee: Sofradir Co.
• Original Assignee: Thomson-CSF
• Inventors: Duboz, Jean-Yves, Bois, Philippe, Rosencher, Emmanuel
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/549,812
• Time in Patent Office: 824 Days
• Field of Search: 257/777-781, 257/737, 257/738, 257/723, 257/730, 257/735, 257/668, 257/693
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 27/1465 of the hybrid type
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H01L 2924/381 Pitch distance

Abstract

Semiconductor hybrid components, especially linear infrared detectors produced by hybridization. A main substrate has integrated thereon active elements which cannot be produced on a silicon substrate. The substrate is made, for example, of AsGa, InP, HgCdTe or PbTe. Several silicon chips are mounted on the main substrate, by hybridization using indium balls. These chips include the read and multiplexing circuits. The silicon chips remain of limited size (a few millimeters) so that the differential thermal expansion stresses are limited, but the detection array may be produced as one piece without butt-joining. It is therefore possible to produce arrays of great length (several centimeters) and of high resolution (at least a thousand points).

Claims

1. A hybrid semiconductor component comprising:

a main substrate made of a material other than silicon and having an inside surface area including an integrated array of a plurality of radiation responsive elements and a separate portion having a plurality of substrate contact pads with conductive connections being provided between at least some of the said radiation responsive elements and at least some of the substrate contact pads; and

a plurality of silicon chips, each said silicon chip having an area smaller than that of the inside surface area of the main substrate and each said silicon chip containing at least one integrated circuit connected to chip contact pads, with at least some of the chip contact pads being bonded to facing ones of the substrate contact pads without any of said silicon chips overlying the integrated array of radiation responsive elements.

2. A hybrid component according to claim 1, wherein the radiation responsive elements of the main substrate are distributed along at least one line in said inside surface area and the respective substrate contact pads connected to said active elements are distributed in several groups located away from the inside surface area which contains said at least one line in said separate portion and, wherein each group of the several groups corresponds to a respective silicon chip with a size and pitch of the substrate contact pads in each said group being larger than a size and pitch of the corresponding active elements.

3. A hybrid component according to claim 1, wherein the radiation responsive elements are photosensitive elements.

4. A hybrid component according to claim 3, wherein the photosensitive elements are infrared elementary detectors.

5. A hybrid component according to claim 4, wherein the integrated array includes a linear or multilinear array of infrared detectors on the main substrate in said inside surface area and each of the plurality of silicon chips includes read circuits corresponding to each infrared detector in order to read charges generated by illumination of the infrared detectors.

6. A hybrid component according to claim 5, wherein the integrated array of infrared detectors is illuminated via a front face of the main substrate on which the integrated array of infrared detectors are provided and to which the plurality of silicon chips are bonded so as not to cover the infrared detectors.

7. A hybrid component according to claim 1, wherein the plurality of silicon chips have lateral dimensions of less than 10 millimeters on a side.

8. A hybrid component according to claim 1, wherein the plurality of silicon chips are bonded to the main substrate by means of indium balls formed on the facing substrate contact pads.

9. A hybrid component according to claim 1, wherein the main substrate is made of a semiconductor material selected from the group consisting of GaAs, InP, HgCdTe, and Pbte.

10. A hybrid component according to claim 1, further including a plurality of external connection pads for connecting said hybrid semiconductor component with other external devices, said external connection substrate pads being provided at a peripheral portion of said main substrate which is removed from the radiation responsive elements in the integrated array and the silicon chips.

11. A hybrid component according to claim 10, wherein said external connection pads are conductively connected to additional substrate contact pads bonded to the silicon chips.

12. A hybrid component according to claim 10, wherein the radiation responsive elements of the main substrate are distributed along at least one line in said inside surface area and the respective substrate contact pads connected to said radiation responsive elements are distributed in several groups located away from the inside surface area which contains said at least one line in said separate portion, and wherein each group of the several groups corresponds to a respective silicon chip with a size and pitch of the substrate contact pads in each said group being larger than a size and pitch of the corresponding radiation responsive elements.

13. A hybrid component according to claim 11, wherein the radiation responsive elements of the main substrate are distributed along at least one line in said inside surface area and the respective substrate contact pads connected to said radiation responsive elements are distributed in several groups located away from the inside surface area which contains said at least one line in said separate portion, and wherein each group of the several groups corresponds to a respective silicon chip with a size and pitch of the substrate contact pads in each said group being larger than a size and pitch of the corresponding radiation responsive elements.

14. A hybrid component according to claim 10, wherein the radiation responsive elements are photosensitive elements.

15. A hybrid component according to claim 11, wherein the radiation responsive elements are photosensitive elements.

16. A hybrid component according to claim 2, wherein the radiation responsive elements are photosensitive elements.

17. A hybrid component according to claim 14, wherein the photosensitive elements are infrared elementary detectors.

18. A hybrid component according to claim 15, wherein the photosensitive elements are infrared elementary detectors.

19. A hybrid component according to claim 16, wherein the photosensitive elements are infrared elementary detectors.

20. A hybrid component according to claim 5, wherein the integrated array of infrared detectors is illuminated via a front face of the main substrate on which the integrated array of infrared detectors are provided and to which the plurality of silicon chips are bonded so as not to cover the infrared detectors.