Differential-to-CMOS level converter having cross-over voltage adjustment

• US 5,726,588 A
• Filed: 08/15/1996
• Issued: 03/10/1998
• Est. Priority Date: 03/12/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Fiedler, Alan
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/698,306
• Time in Patent Office: 572 Days
• Field of Search: 326/21, 326/33, 326/63, 326/68, 326/71-73, 327/52, 327/73, 327/78
• US Class Current: 326/63
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03K 5/249 using clock signals
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

A differential-to-CMOS level converter includes a differential-to-CMOS conversion circuit, first and second buffers and a cross-over adjustment circuit. The conversion circuit has first and second differential input terminals and first and second complementary output terminals. The first buffer has a buffer input coupled to the first complementary output and has a buffer output. The second buffer has a buffer input coupled to the second complementary output and has a buffer output. The cross-over adjustment circuit has first and second voltage measurement inputs coupled to the first and second buffer outputs and has first and second offset current outputs coupled to the first and second buffer inputs, respectively.

Claims

1. A differential-to-CMOS level converter comprising:

a conversion circuit having first and second differential inputs and first and second complementary outputs; and

a cross-over adjustment circuit having first and second cross-over voltage measurement inputs coupled to the first and second complementary outputs and having first and second offset current outputs coupled to the first and second complementary outputs, respectively.

2. The differential-to-CMOS level converter of claim 1 and further comprising:

a first buffer coupled between the first complementary output and the first cross-over voltage measurement input; and

a second buffer coupled between the second complementary output and the second cross-over voltage measurement input.

3. The differential-to-CMOS level converter of claim 2 wherein the first and second buffers each comprise first and second CMOS inverters coupled in series with one another.

4. The differential-to-CMOS level converter of claim 1 wherein the cross-over adjustment circuit comprises:

first and second supply terminals;

a cross-over voltage reference node;

a cross-over voltage measurement circuit comprising a pull-up circuit coupled between the first supply terminal and a cross-over adjustment output and controlled by the first and second cross-over voltage measurement inputs, and a pull-down circuit coupled between the cross-over adjustment output the second supply terminal and controlled by the first and second cross-over voltage measurement inputs;

a loop filter capacitor coupled to the cross-over adjustment output; and

a differential amplifier having a first amplifier input coupled to the cross-over voltage reference node, a second amplifier input coupled to the cross-over adjustment output and first and second amplifier outputs coupled to the first and second offset current outputs, respectively.

5. The differential-to-CMOS level converter of claim 4 wherein:

the pull-up circuit comprises first and second P-channel transistors coupled together in series between the first supply terminal and the cross-over adjustment output and having gates coupled to the first and second cross-over voltage measurement inputs, respectively; and

the pull-down circuit comprises first and second N-channel transistors coupled together in series between the cross-over adjustment output and the second supply terminal and having gates coupled to the first and second cross-over voltage measurement inputs, respectively.

6. The differential-to-CMOS level converter of claim 4 wherein:

the pull-up circuit comprises;

a first P-channel MOSFET having a gate, source and drain, with the gate coupled to the first cross-over voltage measurement input and the drain coupled to the cross-over adjustment output;

a second P-channel MOSFET having a gate, source and drain, with the gate coupled to the second cross-over voltage measurement input and the drain coupled to the source of the first P-channel MOSFET;

a third P-channel MOSFET having a gate, source and drain, with the gate coupled to the second cross-over voltage measurement input and the drain coupled to the cross-over adjustment output;

a fourth P-channel MOSFET having a gate, source and drain, with the gate coupled to the first cross-over voltage measurement input and the drain coupled to the source of the third P-channel MOSFET; and

a pull-up resistor coupled between the first supply terminal and the sources of the second and fourth P-channel MOSFETs; and

the pull-down circuit comprises;

a first N-channel MOSFET having a gate, source and drain, with the gate coupled to the first cross-over voltage measurement input and the drain coupled to the cress-over adjustment output;

a second N-channel MOSFET having a gate, source and drain, with the gate coupled to the second cross-over voltage measurement input and the drain coupled to the source of the first N-channel MOSFET;

a third N-channel MOSFET having a gate, source and drain, with the gate coupled to the second cress-over voltage measurement input and the drain coupled to the cross-over adjustment output;

a fourth N-channel MOSFET having a gate, source and drain, with the gale coupled to the first cross-over voltage measurement input and the drain coupled to the source of the third N-channel MOSFET; and

a pull-down resistor coupled between the sources of the second and fourth N-Channel MOSFETS and the second supply terminal.

7. The differential-to-CMOS level converter of claim 4 wherein the loop capacitor comprises:

a P-channel MOSFET having a gate coupled to the cross-over adjustment output and a source and drain coupled to the first supply terminal; and

an N-channel MOSFET having a gate coupled to the cross-over adjustment output and a source and drain coupled to the second supply terminal.

8. The differential-to-CMOS level converter of claim 4 wherein the cross-over adjustment circuit further comprises a voltage reference filter capacitor coupled to the cross-over voltage reference node.

9. The differential-to-CMOS level converter of claim 4 wherein the cross-over adjustment circuit further comprises a first diode-connected transistor coupled between the first supply terminal and the cross-over voltage reference node and a second diode-connected transistor coupled between the cross-over reference voltage node and the second supply terminal.

10. The differential-to-CMOS level converter of claim 4 wherein the differential-to-CMOS level converter further comprises:

a first current sink comprising a first current mirror having an input coupled to the first amplifier output and an output coupled to the first offset current output;

a second current sink comprising a second current mirror having an input coupled to the first amplifier output and an output coupled to the second offset current output;

a first current source comprising a third current mirror having an input coupled to the second amplifier output and an output coupled to the first offset current output; and

a second current source comprising a fourth current mirror having an input coupled to the second amplifier output and an output coupled to the second offset current output.

11. The differential-to-CMOS level converter of claim 10 wherein the first and second current mirrors comprise N-channel current mirrors and wherein the converter further comprises:

a fifth current mirror coupled between the first amplifier output and the inputs of the first and second current mirrors, wherein the fifth current mirror comprises a P-channel current mirror.

12. A integrated circuit comprising:

first and second supply terminals;

a differential-to-CMOS converter coupled between the first and second supply terminals and having first and second differential inputs and first and second complementary outputs; and

a cross-over adjustment circuit having first and second cross-over voltage measurement inputs coupled to the first and second complementary outputs, respectively, and having first and second offset current outputs coupled to the first and second complementary outputs, respectively.

13. The integrated circuit of claim 12 and further comprising:

a first buffer coupled between the first complementary output and the first cross-over voltage measurement input; and

a second buffer coupled between the second complementary output and the second cross-over voltage measurement input.

14. A method of adjusting a cross-over voltage of first and second complementary outputs of a differential-to-CMOS level converter, the method comprising:

generating first and second buffered outputs as a function of the first and second complementary outputs, respectively;

measuring a cross-over voltage of the first and second buffered outputs;

comparing the cross-over voltage to a reference voltage;

sourcing current into the first and second complementary outputs if the cross-over voltage is below the reference voltage; and

sinking current from the first and second complementary outputs if the cross-over voltage is above the reference voltage.