Phase locked loop using a counter and a microcontroller to produce VCXO control signals

• US 5,726,607 A
• Filed: 02/04/1994
• Issued: 03/10/1998
• Est. Priority Date: 06/15/1992
• Status: Expired due to Term

• Current Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Original Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Inventors: Ott, James W., Opoczynski, Adam, Brede, Jeffrey
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/192,071
• Time in Patent Office: 1,495 Days
• Field of Search: 331/2, 331/14, 331/17, 331/25
• US Class Current: 331/2
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/146 by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master

Abstract

A digitally controlled phase locked loop generates a derived clock signal that is frequency locked to a reference clock signal. The apparatus is comprised of a microcontroller, counter, digital to analog converter (DAC) and a voltage controlled crystal oscillator (VCXO) connected in a feedback loop arrangement. A frequency output derived from the VCXO periodically samples an incoming reference signal. The sampled count value is compared to an ideal count value associated with the same sampling time period. A microcontroller and software-based algorithm perform the phase comparison and loop filter operations of the phase locked loop (PLL).

Claims

1. A clock system, comprising:

first clock means for generating a first derived clock signal that is frequency locked to a reference clock signal; and

second clock means for generating a second derived clock signal that is frequency locked to the reference clock signal;

wherein each of the first and second clock means comprise;

a voltage controlled oscillator for generating the respective derived clock signal;

a counter, connected to the oscillator for receiving the respective derived clock signal and the reference clock signal, and for counting a number of pulses of the reference clock signal occurring over a predetermined number of clock periods of the respective derived clock signal; and

controller means, connected to the counter and to the oscillator such that the counter, the controller means and the oscillator are connected in a feedback arrangement, for comparing the counted number of pulses of the reference clock signal with an ideal count value, and for generating a control voltage in proportion to a difference obtained therefrom, and wherein the control voltage is applied to the oscillator such that the frequency of the respective derived clock signal varies in a direction which more closely approximates the frequency of the reference clock signal.

2. The system of claim 1 wherein each of the first and second clock means further includes:

phase align means, connected between the oscillator and the counter to receive the respective derived clock signal, and further connected to receive the other derived clock signal, for comparing the phases of the first and second derived clock signals and for shifting the phase of either the first or second derived clock signal such that the phase difference between the first and second derived clock signals approaches 0°

.

3. The system according to claim 1, wherein the first and second clock means are connected in a protection configuration in which one of the first or second clock means is designated as an active clock circuit means and the other clock means is designated as a standby clock circuit means, such that in the event of failure of the active clock circuit means, the active clock means can be switched out and the standby clock circuit means can be designated as the active clock circuit means.

4. The system according to claim 3 including switch means, connected between the first and second clock means, for monitoring the first and second clock means and for controlling which of the first or second clock means is designated as the active clock circuit means and which of the first or second clock means is designated as the standby clock circuit means.

5. A clock system, comprising:

first clock circuit means for generating a first derived clock signal that is frequency locked to a reference clock signal; and

second clock circuit means for generating a second derived clock signal that is frequency locked to the reference clock signal;

wherein each of the first and second clock circuit means comprise;

an oscillator for generating the respective derived clock signal, the respective derived clock signal having a frequency dependent on a control voltage applied to the oscillator;

a counter, connected to the oscillator, for receiving the respective derived clock signal and the reference clock signal, and for counting a number of pulses of the reference clock signal occurring over a sample period, said sample period defined as a predetermined number of clock periods of the respective derived clock signal;

controller means, connected to the counter and to the oscillator such that the counter, the controller means and the oscillator are connected in a feedback arrangement, for comparing the counted number of pulses of the reference clock signal with an ideal count value corresponding to an ideal frequency, for accumulating the differences obtained therefrom over a predetermined number of sample periods and for generating the control voltage that is proportional to the accumulated difference, wherein the control voltage is applied to the oscillator such that the frequency of the respective derived clock signal varies in a direction which more closely approximates the frequency of the reference clock signal; and

phase align means, connected between the oscillator and the counter to receive the respective derived clock signal, and further connected to receive the other derived clock signal, for comparing the phases of the first and second derived clock signals, producing a control signal in relation to the difference obtained therefrom, and for shifting the phase of the first or second derived clock signal in response to the control signal such that the phase difference between the first and second derived clock signals approaches 0°

.

6. The system according to claim 5, wherein the first and second clock circuit means are connected in a protection configuration in which one of the first or second clock circuit means is designated as an active clock circuit means and the other clock circuit means is designated as a standby clock circuit means, wherein only the active clock circuit means is providing the system clock signal, and wherein in the event of failure of the active clock circuit means, the standby clock circuit acts as the active clock circuit means.

12. A system according to claim 5 further wherein the controller means includes means for generating the derived clock signal in a hold-over mode of operation unsynchronized to the reference signal, and further wherein the phase align means includes means for causing said controller means to switch to the hold-over mode of operation prior to phase aligning the first and second derived clock signals.

13. The system according to claim 6, wherein the standby clock circuit means is switched for the active clock circuit means during an interval of time of nontransition by the active clock circuit means and the standby clock circuit means.

7. A clock system, comprising:

a first clock adapted to generate a first derived clock signal that is frequency locked to a reference clock signal; and

a second clock adapted to generate a second derived clock signal that is frequency locked to the reference clock signal;

wherein each of the first and second clocks comprise;

a voltage controlled oscillator which outputs the respective derived clock signal, wherein the respective derived clock signal has a frequency dependent on a control voltage applied to the oscillator;

a counter, connected to receive the respective derived clock signal and the reference clock signal, said counter adapted to count a number of pulses of the reference clock signal occurring over a sample period, wherein said sample period is defined as a predetermined number of clock periods of the respective derived clock signal;

a controller, connected to the counter and to the oscillator such that the counter, the controller and the oscillator are connected in a feedback arrangement; and

a phase aligner, connected between the oscillator and the counter to receive the respective derived clock signal, and further connected to receive the other derived clock signal;

wherein said controller further includes;

comparator means for comparing the counted number of pulses of the reference clock signal with an ideal count value corresponding to an ideal frequency;

accumulator means for accumulating the differences obtained therefrom over a predetermined number of sample periods; and

means for generating the control voltage, wherein said control voltage is proportional to the accumulated differences, and wherein the control voltage is applied to the oscillator such that the frequency of the respective derived clock signal varies in a direction which more closely approximates the frequency of the reference clock signal;

wherein said phase aligner further includes;

phase comparator means for comparing the phases of the first and second derived clock signals and for producing a control signal in relation to the difference obtained therefrom; and

phase shift means for shifting the phase of the first or second derived clock signal in response to the control signal such that the phase difference between the first and second derived clock signals approaches 0°

.

8. An apparatus for frequency locking a derived clock signal to a reference clock signal, comprising:

a voltage controlled oscillator for generating the derived clock signal;

a counter, connected to receive the derived and reference clock signals, the counter adapted to count a number of pulses of the reference clock signal occurring over a predetermined number of dock periods of the derived clock signal; and

controller means, connected to the counter and to the oscillator such that the counter, the controller means and the oscillator are connected in a feedback arrangement, for comparing the counted number of pulses of the reference clock signal with an ideal count value, and for generating a control signal in proportion to a difference obtained therefrom, wherein the control signal is applied to the oscillator such that the frequency of the derived clock signal varies in a direction which more closely approximates the frequency of the reference clock signal;

the controller means further including means for capturing an initial measurement of the error between the reference clock signal and the derived clock signal and making an initial adjustment to the control signal and calibrating one or more loop gain coefficients to be used in subsequent updates of the control signal.

9. The apparatus of claim 8 further wherein said controller means includes a second means for determining the accuracy of the loop gain coefficients and making an adjustment thereto.

10. The apparatus of claim 9 further wherein said controller means includes means for operating in a normal mode wherein the loop gain coefficients are used for determining corrections to the control signal.

14. The system according to claim 10, wherein the normal mode operates at a first update rate that is faster than a second update rate utilized by the capturing means and the second means for determining the accuracy of the loop gain coefficients.

11. An apparatus for frequency locking a derived dock signal to a reference clock signal, comprising:

a voltage controlled oscillator for generating the derived clock signal;

a counter, connected to receive the derived and reference clock signals, the counter adapted to count a number of pulses of the reference clock signal occurring over a predetermined number of clock periods of the derived clock signal; and

controller means, connected to the counter and to the oscillator such that the counter, the controller means and the oscillator are connected in a feedback arrangement, for comparing the counted number of pulses of the reference clock signal with an ideal count value, and for generating a control signal in proportion to a difference obtained therefrom, wherein the control signal is applied to the oscillator such that the frequency of the derived clock signal varies in a direction which more closely approximates the frequency of the reference clock signal;

the controller means further including means for capturing an initial measurement of the error between the reference clock signal and the derived clock signal and making an initial adjustment to the control signal and calibrating one or more loop gain coefficients to be used in subsequent updates of the control signal; and

the controller means further including means for controlling the control signal to cause the signal to dither the difference between the counted number of pulses and ideal count value.