Power bus having power slits embodied therein and method for making the same

• US 5,726,904 A
• Filed: 06/19/1996
• Issued: 03/10/1998
• Est. Priority Date: 02/10/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Lin, Chong Ming, Hoang, Hy, Chuang, Tatao, Long, Tran
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/665,846
• Time in Patent Office: 629 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/483, 364/492, 364/480, 395/500, 395/750, 250/492.2, 250/492.3, 257/685, 257/678, 257/690, 257/691, 361/736
• US Class Current: 257/773
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90° angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together/resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called "holes", can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.

Claims

1. A method for generating power slits in a power bus located on a chip, comprising the steps of:

(a) receiving parameters indicating coordinate value locations for the chip;

(b) locating the power bus in a defined region of the chip;

(c) determining a width for the power bus;

(d) determining a length for the power bus;

(e) dividing said width of the power bus by a predetermined maximum width of the power slits plus a predetermined first spacing distance between the power slits to determine a first number of power slits to be generated in a horizontal direction of the power bus;

(f) dividing said length of the power bus by a predetermined minimum length of the power slits plus a predetermined second spacing distance between the power slits in the lengthwise direction to determine a second number of power slits to be generated in a vertical direction of the power bus; and

(g) pre-etching the power slits in said horizontal and vertical directions of the power bus according to said first and second numbers of power slits calculated in steps (e) and (f), respectively.

2. A method according to claim 1, wherein said steps (c) and (d) further comprise the steps of:

(i) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in a horizontal direction;

(ii) subtracting said starting-point from said endpoint resulting in a first absolute value;

(iii) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in a vertical direction;

(iv) subtracting said starting-point and said endpoint resulting in a second absolute value;

(v) comparing said first value with said second value to determine which is greater;

(vi) assigning said greater value as said length of the power bus; and

(vii) assigning which ever value is smaller according to step (v) as said width of the power bus.

3. A method according to claim 2, wherein said starting-points and said endpoints are coordinate locations obtained from said coordinate values received in step (a).

4. A method according to claim 1, wherein said step (c) further comprises the steps of comparing said width to a minimum standard value and returning to step (b) if said minimum standard value is greater than said width for the power bus.

5. A method for generating power slits, comprising the steps of:

(a) receiving parameters indicating coordinate value locations for a chip;

(b) locating a power bus in a defined region of said chip;

(c) determining a width for said power bus;

(d) determining a length for said power bus;

(e) dividing said width of said power bus by a predetermined maximum width of the power slits plus a predetermined first spacing distance between the power slits to determine a first number of power slits to be generated in a horizontal direction of said power bus;

(f) dividing said length of said power bus by a predetermined minimum length of the power slits plus a predetermined second spacing distance between the power slits in the lengthwise direction to determine a second number of power slits to be generated in a vertical direction of said power bus;

(g) pre-etching the power slits in said horizontal and vertical directions of said power bus according to said first and second numbers of power slits calculated in steps (e) and (f), respectively; and

(h) repeating steps (a) through (g) until all power buses in said defined region have power slits.

6. A method according to claim 5, further comprising the steps of:

(i) identifying if any power buses in said defined region overlap to form an orthogonal cross section;

(j) removing all power slits in said orthogonal cross section;

(k) extending first pointer line(s) from a first power slit(s) of a first power bus to an opposite boundary side of said cross section to connect said first power slits(s) of said first power bus;

(l) extending second pointer line(s) from a second power slit(s) of a second power bus to an opposite boundary side of said cross section from said second power slits of said second power bus;

(m) intersecting, logically, said first pointer line(s) with said second pointer line(s) forming a defined hole indicating where to generate power slits; and

(n) generating power slit(s) where said defined holes are located.

7. A method according to claim 6, wherein said step (m) comprises the step of logically ANDing, said first pointer line(s) with said second pointer line(s) to form defined holes indicating where to generate power slits.

8. A method according to claim 6, wherein said step (i) comprises the step of evaluating logically where two buses share coordinate values that intersect.

9. A method according to claim 8, wherein said evaluating step includes searching for two buses that have overlapping coordinate values.

10. A method according to claim 6, wherein said extending step in said step (k) includes extending pointer lines in a 90°

direction.

11. A method according to claim 6, wherein said extending step in said step (k) includes extending pointer lines in a 180°

direction.

12. A method according to claim 6, wherein said extending step in said step (l) includes extending pointer lines in a 90°

direction.

13. A method according to claim 6, wherein said extending step in said step (l) includes extending pointer lines in a 180°

direction.

14. A power bus, comprising:

a first axis and a second axis, wherein power flows in the direction of said first axis; and

a plurality of power slits located along said first axis and said second axis of the power bus, wherein said power slits are formed by the steps of;

(a) determining a width for the power bus;

(b) determining a length for the power bus;

(c) dividing said width of the power bus by a predetermined maximum width of said power slits plus a predetermined first spacing distance between said power slits to determine a first number of power slits to be generated in a horizontal direction of the power bus;

(d) dividing said length of the power bus by a predetermined minimum length of said power slits plus a predetermined second spacing distance between said power slits in the lengthwise direction to determine a second number of power slits to be generated in a vertical direction of the power bus; and

(e) pre-etching said power slits in said horizontal and vertical directions of the power bus according to said first and second numbers of power slits calculated in steps (c) and (d), respectively.

15. A power bus according to claim 14, wherein said steps (c) and (d) further comprise the steps of:

(i) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in a horizontal direction;

(ii) subtracting said starting-point from said endpoint resulting in a first absolute value;

(iii) assigning a starting-point and an endpoint corresponding to boundaries of the power bus in a vertical direction;

(iv) subtracting said starting-point and said endpoint resulting in a second absolute value;

(v) comparing said first value with said second value to determine which is greater;

(vi) assigning said greater value as said length of the power bus; and

(vii) assigning which ever value is smaller according to step (v) as said width of the power bus.

16. A power bus according to claim 15, wherein said starting-points and said endpoints are coordinate values obtained from a mask layout data base.