Tool, system and method for dynamic timing analysis in a plural-instance digital system simulation
First Claim
1. For use with a logic simulator wherein one or more defined logic cell(s) contain(s) plural interconnected primitives, a method for performing timing analysis on pins at the boundary of the cell, said method comprising the steps of:
- defining plural bitfields for each pin at the boundary of the cell, each of plural bits of which corresponds with a timing parameter of the cell, with a first bitfield representing the timing parameters associated with a former state of a given pin, with a second bitfield representing the timing parameters associated with a present state of the given pin that is different from the former state of the given pin, and with a third bitfield representing the timing parameters associated with a stable state of the given pin; and
producing a bitwise logic combination of such plural bitfields for a selected one or more of the pins; and
determining the timing of state changes of the pins based upon such logic combination.
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Abstract
Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times. In accordance with a preferred embodiment of the invention, a set of rules is enforced by the logic processor during a digital logic simulation run to ensure that appropriate timing and constraint for the logic cell is maintained. Zero-delay timing is used across a collection of instances within a logic cell, thereby to ensure that all timing and constraint analysis is performed at cell boundaries. Timing is evaluated after all simulation activity for a given time frame has ceased, and such is done preferably by scheduling scrubber events that are executed as tasks on a defer queue that is processed at the end of the digital logic simulation activity.
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Citations
29 Claims
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1. For use with a logic simulator wherein one or more defined logic cell(s) contain(s) plural interconnected primitives, a method for performing timing analysis on pins at the boundary of the cell, said method comprising the steps of:
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defining plural bitfields for each pin at the boundary of the cell, each of plural bits of which corresponds with a timing parameter of the cell, with a first bitfield representing the timing parameters associated with a former state of a given pin, with a second bitfield representing the timing parameters associated with a present state of the given pin that is different from the former state of the given pin, and with a third bitfield representing the timing parameters associated with a stable state of the given pin; and producing a bitwise logic combination of such plural bitfields for a selected one or more of the pins; and determining the timing of state changes of the pins based upon such logic combination. - View Dependent Claims (2, 3)
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4. A timing analysis tool for use with a logic simulator for performing timing analysis on pins at the boundary of a logic cell which contains plural interconnected primitives comprising:
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means for storing timing statements corresponding to each pin at the boundary of the cell; bitfield means which include a bitfield array associated with each pin, wherein each array includes plural bits grouped into bitfields and wherein the bitfields are organized into bitfield sets wherein each set corresponds to a logic state that a pin may achieve, and further wherein each bitfield set includes a bitfield associated with a former state of a given pin, a bitfield associated with a present state of a given pin, and a bitfield associated with a stable state of a given pin; means for performing bitwise logic combinations of the bitfields for a selected one or more of the pins to produce a bitfield result; and means for selecting timing statements according to the bitfield result and determining the timing of state changes of the pins. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. In a logic simulator wherein one or more defined logic cells include(s) cell pins at the boundary thereof, and contain(s) one or more interconnected primitives, a method for selecting timing statements which characterize a particular cell'"'"'s timing behavior comprising the steps of:
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storing plural timing statements in simulator-accessible memory, wherein each timing statement has a designated value; defining plural bitfields for each cell pin wherein each bitfield includes plural bits which correspond to the timing statements, and further wherein each logic state which may be achieved by a pin is characterized by a set of bitfields which include a bitfield associated with a former state of a given pin, a new state of the given pin, and a stable state of the given pin; processing bitfield values to determine a result bitfield value which corresponds to one or more of the timing statements; and deferring processing of selected bitfields, when a cell pin changes state, until after the completion of all simulation activity in a cell for a given time. - View Dependent Claims (17, 18, 19, 20, 21)
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22. In a logic simulator wherein one or more defined logic cell(s) include cell pins at the boundary thereof, and contain(s) one or more interconnected primitives, a method for selecting timing statements for the logic simulator which characterize a particular cell'"'"'s timing behavior comprising the steps of:
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storing plural timing statements in simulator-accessible memory, wherein each timing statement has a designator; defining plural bitfields for each cell pin wherein each bitfield includes plural bits having ordered values, wherein each ordered value corresponds to a timing statement designator, and further wherein each logic state which may be achieved by a pin is characterized by a set of bitfields which include a bitfield associated with a former state of a given pin, a new state of the given pin, and a stable state of the given pin; processing selected bitfields to determine a result bitfield which includes one or more bits set to a pre-defined value; and selecting the timing statements whose designators match the ordered value of the bits which have been set to the pre-defined value in the result bitfield. - View Dependent Claims (23, 24, 25, 26)
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27. A timing analysis system for use with a logic simulator for performing timing analysis on pins at the boundary of a logic cell which contains one or more primitives comprising:
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a first data structure for storing plural bitfield arrays wherein each array corresponds to a cell pin and is characterized by having at least one bitfield set which corresponds to a logic state which may be achieved by the corresponding pin, and wherein each bitfield set includes a bitfield associated with the former state of the pin, a bitfield associated with the present state of the pin, and a bitfield associated with the stable state of the pin; a processor operatively coupled to the first data structure for receiving selected bitfield values and performing bitwise logic combination of such selected values; and a second data structure operatively coupled to the processor for storing timing parameters selectable by the processor for use by the logic simulator. - View Dependent Claims (28, 29)
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Specification