Tool, system and method for dynamic timing analysis in a plural-instance digital system simulation

• US 5,726,918 A
• Filed: 06/05/1995
• Issued: 03/10/1998
• Est. Priority Date: 06/05/1995
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Roth, Thomas E., Kozber, Oliver W., Giramma, David J.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/463,881
• Time in Patent Office: 1,009 Days
• Field of Search: 364/488, 364/489, 364/578, 395/500
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times. In accordance with a preferred embodiment of the invention, a set of rules is enforced by the logic processor during a digital logic simulation run to ensure that appropriate timing and constraint for the logic cell is maintained. Zero-delay timing is used across a collection of instances within a logic cell, thereby to ensure that all timing and constraint analysis is performed at cell boundaries. Timing is evaluated after all simulation activity for a given time frame has ceased, and such is done preferably by scheduling scrubber events that are executed as tasks on a defer queue that is processed at the end of the digital logic simulation activity.

Claims

1. For use with a logic simulator wherein one or more defined logic cell(s) contain(s) plural interconnected primitives, a method for performing timing analysis on pins at the boundary of the cell, said method comprising the steps of:

defining plural bitfields for each pin at the boundary of the cell, each of plural bits of which corresponds with a timing parameter of the cell, with a first bitfield representing the timing parameters associated with a former state of a given pin, with a second bitfield representing the timing parameters associated with a present state of the given pin that is different from the former state of the given pin, and with a third bitfield representing the timing parameters associated with a stable state of the given pin; and

producing a bitwise logic combination of such plural bitfields for a selected one or more of the pins; and

determining the timing of state changes of the pins based upon such logic combination.

2. The method of claim 1 which further comprises the step of deferring said determining step to accommodate propagation delays through the plural interconnected primitives to the pins at the boundary of the cell.

3. The method of claim 1 wherein said determining step includes evaluating the produced logic combination in order to determine any timing violations.

4. A timing analysis tool for use with a logic simulator for performing timing analysis on pins at the boundary of a logic cell which contains plural interconnected primitives comprising:

means for storing timing statements corresponding to each pin at the boundary of the cell;

bitfield means which include a bitfield array associated with each pin, wherein each array includes plural bits grouped into bitfields and wherein the bitfields are organized into bitfield sets wherein each set corresponds to a logic state that a pin may achieve, and further wherein each bitfield set includes a bitfield associated with a former state of a given pin, a bitfield associated with a present state of a given pin, and a bitfield associated with a stable state of a given pin;

means for performing bitwise logic combinations of the bitfields for a selected one or more of the pins to produce a bitfield result; and

means for selecting timing statements according to the bitfield result and determining the timing of state changes of the pins.

5. The tool of claim 4 which further comprises means for deferring the selection of timing statements to accommodate propagation delays through the plural interconnected primitives at the boundary of the cell.

6. The tool of claim 5, wherein said means for deferring includes a task queue for scheduling said deferring step for execution at a definedly later time.

7. The tool of claim 4, wherein said means for storing timing statements includes a data structure wherein each timing statement is indexed with a designated value.

8. The tool of claim 7, wherein the timing statements include at least one statement which characterizes an output-to-output delay.

9. The tool of claim 7, wherein the timing statements include at least one statement which characterizes a constraint.

10. The tool of claim 9, wherein the constraint is a set up time which constrains a pin to be stable for a defined amount of time prior to a change on another pin.

11. The tool of claim 9, wherein the constraint is a hold time which constrains a pin to be stable for a defined time after a change on another pin.

12. The tool of claim 9, wherein the constraint is a minimum pulse width which constrains two consecutive transitions on a pin to occur no closer than a defined amount of time.

13. The tool of claim 4, wherein said bitfield means includes a data structure.

14. The tool of claim 4, wherein said means for performing bitwise logic combinations includes a logic processor operatively coupled to the bitfield means, said logic processor being capable of being loaded with selected bitfield values.

15. The tool of claim 4, wherein said means for selecting timing statements includes a memory-based look-up table containing one or more such timing statements each having associated therewith a table index by which such timing statements may be selected.

16. In a logic simulator wherein one or more defined logic cells include(s) cell pins at the boundary thereof, and contain(s) one or more interconnected primitives, a method for selecting timing statements which characterize a particular cell'"'"'s timing behavior comprising the steps of:

storing plural timing statements in simulator-accessible memory, wherein each timing statement has a designated value;

defining plural bitfields for each cell pin wherein each bitfield includes plural bits which correspond to the timing statements, and further wherein each logic state which may be achieved by a pin is characterized by a set of bitfields which include a bitfield associated with a former state of a given pin, a new state of the given pin, and a stable state of the given pin;

processing bitfield values to determine a result bitfield value which corresponds to one or more of the timing statements; and

deferring processing of selected bitfields, when a cell pin changes state, until after the completion of all simulation activity in a cell for a given time.

17. The method of claim 16, wherein said processing step is performed by a logic processor which holds a bitfield value for each pin associated with the pin'"'"'s current status, and is capable of performing bitwise logic combination of such plural bitfield values to arrive at the result bitfield.

18. The method of claim 17, wherein said processing step includes the step of classifying each pin as

either an update pin, in which case the logic processor is loaded with the stable state bitfield value for the new state,

or an evaluate pin, in which case the logic processor is loaded with a bitfield value which indicates the transition made by the pin.

19. The method of claim 18, wherein said deferring step is accomplished at least in part by defining a time queue and scheduling a 0-delay event onto the queue when a cell pin changes state.

20. The method of claim 19, wherein said time queue is processed by the logic processor after all other simulation activity for a cell is completed.

21. The method of claim 16, wherein there is a one-to-one correspondence between the number of bits in a bitfield and the number of timing statements.

22. In a logic simulator wherein one or more defined logic cell(s) include cell pins at the boundary thereof, and contain(s) one or more interconnected primitives, a method for selecting timing statements for the logic simulator which characterize a particular cell'"'"'s timing behavior comprising the steps of:

storing plural timing statements in simulator-accessible memory, wherein each timing statement has a designator;

defining plural bitfields for each cell pin wherein each bitfield includes plural bits having ordered values, wherein each ordered value corresponds to a timing statement designator, and further wherein each logic state which may be achieved by a pin is characterized by a set of bitfields which include a bitfield associated with a former state of a given pin, a new state of the given pin, and a stable state of the given pin;

processing selected bitfields to determine a result bitfield which includes one or more bits set to a pre-defined value; and

selecting the timing statements whose designators match the ordered value of the bits which have been set to the pre-defined value in the result bitfield.

23. The method of claim 22, wherein said processing step is performed by a logic processor capable of performing bitwise logic combination of the selected bitfields.

24. The method of claim 23 wherein said processing step includes the step of classifying each pin as

either an update pin, in which case the logic processor is loaded with the stable state bitfield value for the new state,

or an evaluate pin, in which case the logic processor is loaded with a bitfield value which indicates the state transition made by the pin.

25. The method of claim 24, wherein the bitfield value for an evaluate pin includes the product of a bitwise AND of the bitfield values of the former state of a pin and the new state of the state to which the pin transitioned, and the subsequent bitwise OR of that product and the bitfield value for the stable state of the state to which the pin transitioned.

26. The method of claims 24 or 25, wherein the result bitfield is defined by the bitwise AND of all bitfield values in the logic processor.

27. A timing analysis system for use with a logic simulator for performing timing analysis on pins at the boundary of a logic cell which contains one or more primitives comprising:

a first data structure for storing plural bitfield arrays wherein each array corresponds to a cell pin and is characterized by having at least one bitfield set which corresponds to a logic state which may be achieved by the corresponding pin, and wherein each bitfield set includes a bitfield associated with the former state of the pin, a bitfield associated with the present state of the pin, and a bitfield associated with the stable state of the pin;

a processor operatively coupled to the first data structure for receiving selected bitfield values and performing bitwise logic combination of such selected values; and

a second data structure operatively coupled to the processor for storing timing parameters selectable by the processor for use by the logic simulator.

28. The system of claim 27, wherein said second data structure includes timing parameters related to the path delay between cell pins.

29. The system of claim 27, wherein said second data structure includes timing parameters related to timing constraints of the cell pins.