Method and apparatus for analog reading values stored in floating gate structures

• US 5,726,934 A
• Filed: 04/09/1996
• Issued: 03/10/1998
• Est. Priority Date: 04/09/1996
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Information Storage Devices, Inc. (Winbond Electronics Corporation)
• Inventors: Tran, Hieu Van, Blyth, Trevor, Yoon, Sukyoon, Brennan, James Jr.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/629,729
• Time in Patent Office: 700 Days
• Field of Search: 365/205, 365/189.01, 365/230.01, 365/185.2, 365/185.21, 365/210, 365/203
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Claims

1. A method of reading an analog value stored in a storage cell having a source, a drain, a gate and a floating gate comprising the steps of:

(a) coupling a first reference voltage to the drain of the storage cell;

(b) coupling a second reference voltage to the gate of the storage cell;

(c) providing an initial load current through the drain and source of the storage cell;

(d) reducing the load current through the drain and source of the storage cell to a value at least one order of magnitude less than the initial load current; and

,

(e) providing a read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through.

2. The method of claim 1 wherein in step (e), the read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through is provided after the read output voltage has substantially stabilized with the reduced load.

3. The method of claim 1 wherein in step (d), the load current through the drain and source of the storage cell is reduced to a value at least two orders of magnitude less than the initial load current.

4. The method of claim 1 wherein in step (d), the load current through the drain and source of the storage cell is reduced to a value approximately three orders of magnitude less than the initial load current.

5. The method of claim 1 wherein in step (d), the load current through the drain and source of the storage cell is reduced to substantially zero current.

6. The method of claim 1 wherein in step (e), a read output voltage responsive to the voltage on the source of the storage cell is provided through a transistor switch to a holding capacitor while the initial load current is provided, and after the current has been reduced, the transistor switch is opened whereupon the read output voltage held by the capacitor is responsive to the voltage on the source of the storage cell with the reduced load current there through.

7. The method of claim 1 wherein the analog value is one of a plurality of discrete values each representing a specific multi-bit digital signal, and further comprising the step of converting the read output voltage to a respective multi-bit signal.

8. Apparatus for reading an analog value stored in a storage cell having a source, a drain, a gate and a floating gate comprising:

means providing a first reference voltage to the drain of the storage cell;

means providing a second reference voltage to the gate of the storage cell;

means providing an initial load current through the drain and source of the storage cell, and then reducing the load current through the drain and source of the storage cell to a value at least one order of magnitude less than the initial load current; and

,

circuitry providing a read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through.

9. The apparatus of claim 8 wherein the circuitry providing a read output voltage is circuitry for providing a read output voltage after the read output voltage has substantially stabilized with the reduced load.

10. The apparatus of claim 8 wherein the means providing an initial load current through the drain and source of the storage cell, is a means reducing the load current through the drain and source of the storage cell to a value at least two orders of magnitude less than the initial load current.

11. The apparatus of claim 8 wherein the means providing an initial load current through the drain and source of the storage cell is a means reducing the load current through the drain and source of the storage cell to a value approximately three orders of magnitude less than the initial load current.

12. The apparatus of claim 8 wherein the means providing an initial load current through the drain and source of the storage cell is a means reducing the load current through the drain and source of the storage cell to substantially zero current.

13. The apparatus of claim 8 wherein the circuitry providing a read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through includes a transistor switch and a holding capacitor, the read output voltage responsive to the voltage on the source of the storage cell being provided through the transistor switch to the holding capacitor while the initial load current is provided, and after the current has been reduced, for opening the transistor switch so that the read output voltage held by the capacitor is responsive to the voltage on the source of the storage cell with the reduced load current there through.

14. The apparatus of claim 8 further comprised of an analog to digital converter coupled to the means for providing a read output voltage to convert the read output voltage to a multi-bit digital signal.

15. A method of reading an analog value stored in a storage cell having a source, a drain, a gate and a floating gate comprising the steps of:

(a) coupling a first reference voltage to the drain of the storage cell;

(b) coupling a second reference voltage to the gate of the storage cell;

(c) providing an initial load current through the drain and source of the storage cell;

(d) reducing the load current of the storage cell through the drain and source of the storage cell; and

(e) providing a read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through.

16. The method of claim 15 wherein in step (e), the read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through is provided after the read output voltage has substantially stabilized with the reduced load.

17. Apparatus for reading an analog value stored in a storage cell having a source, a drain, a gate and a floating gate comprising:

means providing a first reference voltage to the drain of the storage cell;

means providing a second reference voltage to the gate of the storage cell;

means providing an initial load current through the drain and source of the storage cell, and then reducing the load current through the drain and source of the storage cell; and

circuitry providing a read output voltage responsive to the voltage on the source of the storage cell with the reduced load current there through.

18. The apparatus of claim 17 wherein the circuitry providing a read output voltage is circuitry for providing a read output voltage after the read output voltage has substantially stabilized with the reduced load.