Method and arrangement for synchronization in OFDM modulation

• US 5,726,973 A
• Filed: 08/22/1996
• Issued: 03/10/1998
• Est. Priority Date: 01/18/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Telia AB (Government of Norway)
• Inventors: Isaksson, Mikael
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): BNIMOUSSA, ABDELHAMID
• Application Number:
  US08/669,379
• Time in Patent Office: 565 Days
• Field of Search: 370/203, 370/208, 370/484, 370/503, 375/344, 455/192.2, 455/202, 455/257
• US Class Current: 370/203
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2662 Symbol synchronisation
• CPC Class Codes: H04L 27/2665 Fine synchronisation, e.g. by positioning the FFT window

Abstract

A method and an arrangement for synchronization in OFDM modulation. Frequency errors of an IF clock and a sampling clock are controlled by estimating the deviation of the sampling clock and, respectively, the IF clock for two subcarriers with different frequencies. According to the invention, the frequencies are chosen symmetrically around zero and the absolute phase errors are detected for both subcarriers. Timing errors and phase errors are formed from the absolute phase errors in order to generate two control signals. The first control signal is formed from the deviation of the sampling clock and the timing error for controlling the sampling clock while the second control signal is formed from the deviation of the IF clock and the phase error for controlling the IF clock.

Claims

1. A method for synchronization in OFDM (orthogonal frequency division multiplexing) modulation, whereby frequency errors in an IF (intermediate frequency) clock and a sampling clock are controlled by estimating the deviation of the sampling clock and of the IF clock for two subcarriers with different frequencies (k1 and, respectively, k2), comprising:

choosing the different frequencies (k1, k2) symmetrically around zero;

detecting absolute phase errors (θ

1, θ

2) for both subcarriers;

forming a timing error and a phase error from the absolute phase errors (θ

1, θ

2);

forming a first control signal (F1) from the deviation of the sampling clock and the timing error for controlling the sampling clock; and

forming a second control signal (F2) from the deviation of the IF clock and the phase error for controlling the IF clock.

2. A method according to claim 1, wherein the timing error is calculated as the difference between the absolute phase errors (θ

2-θ

1) and the phase error is calculated as the sum of the absolute phase errors (θ

1+θ

2).

3. Method according to claim 2, wherein the first control signal is formed by the sum of the deviation of the sampling clock and the timing error, and

that the second control signal is formed by the sum of the deviation of the IF clock and the phase error.

4. Method according to claim 3, wherein the timing error and the phase error are scaled by a suitable scaling factor before they are added to form respective control signals.

5. Method according to claim 4, wherein the scaling factor is 0.1.

6. Method according to claim 5, wherein the control signals are updated for each OFDM frame.

7. Method according to claim 4, wherein the control signals are updated for each OFDM frame.

8. Method according to claim 3, wherein the control signals are updated for each OFDM frame.

9. Method according to claim 2, wherein the control signals are updated for each OFDM frame.

10. A method according to claim 1, wherein the step of forming the first control signal comprises adding, the deviation of the sampling clock to the timing error, and

wherein the step of forming the second control signal comprises adding the deviation of the IF clock to the phase error.

11. A method according to claim 10, further comprising:

scaling the timing error by a suitable scaling factor before the step of adding the deviation of the sampling clock to the timing error to form the first control signal (F1; and

scaling the phase error by said suitable scaling factor before the step of adding the deviation of the IF clock to the phase error to form the second control signal (F2).

12. A method according to claim 11, wherein the suitable scaling factor is 0.1.

13. Method according to claim 12, wherein the control signals are updated for each OFDM frame.

14. A method according to one of claims 1, 2, 10, 11, and 12 further comprising updating the first and second control signals for each of at least one OFDM frame.

15. Method according to claim 11, wherein the control signals are updated for each OFDM frame.

16. Method according to claim 10, wherein the control signals are updated for each OFDM frame.

17. An arrangement for synchronizing in OFDM modulation, comprising:

a down converter for down conversion of an IF signal to baseband components;

an oscillator with an IF clock, said oscillator controlling said down converter;

an A/D (analog-to-digital) converter for digitization of the baseband components;

an oscillator with a sampling clock, said oscillator with said sampling clock controlling said A/D converter;

an FFT processor for converting the baseband components from the time domain to the frequency domain;

a demultiplexing unit for forming two subcarriers with different frequencies;

elements for forming a deviation of the sampling clock and a deviation of the IF clock;

elements for forming absolute phase errors of the two subcarriers;

elements for forming a timing error from the absolute phase errors;

elements for forming a phase error from the absolute phase errors;

elements for forming a first control signal (F1) from the deviation of the sampling clock and the timing error for controlling the sampling clock; and

elements for forming a second control signal (F2) from the deviation of the IF clock and the phase error for controlling the IF clock.

18. An arrangement according to claim 17, wherein the elements for forming the absolute phase errors include an arc-tan unit, wherein the elements for forming the timing error include an adding unit for forming the difference between the absolute phase errors, wherein the elements for forming the phase error include an adding unit for forming the sum of the absolute phase errors, wherein the elements for forming the first control signal include an adding unit for adding the deviation of the sampling clock to the timing error, and wherein the elements for forming the second control signal include an adding unit for adding the deviation of the IF clock to the phase error.

19. An arrangement according to claim 18, further comprising:

a multiplication unit for multiplying the timing error by a scaling factor before addition of the timing error to the first control signal; and

a multiplication unit for multiplying the phase error by said scaling factor before addition of the phase error to the second control signal.