Multiplexer and demultiplexer

• US 5,726,990 A
• Filed: 04/08/1996
• Issued: 03/10/1998
• Est. Priority Date: 08/10/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimada, Masaaki, Higashisaka, Norio
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): PHILLIPS, MATTHEW
• Application Number:
  US08/629,148
• Time in Patent Office: 701 Days
• Field of Search: 370/532-545, 341/100, 341/101, 327/407, 327/415, 395/891, 364/239.2, 364/939.5
• US Class Current: 370/536
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

A multiplexer includes an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m^n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit vary due to device parameters or temperature, the timing of the data input can be adjusted by the variable delay circuit.

Claims

1. A multiplexer comprising:

an n-th stage as a final output stage (n=integer, 2≦

n);

j stages (j=integer, 1≦

j≦

n-1),

the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal,

a j-th stage including m^n-j-1 (m=integer, 2≦

m) multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, a multiplexer block in the j-th stage being connected to a multiplexer block in the (j+1)-th stage so that the serial data output from a multiplexer block in the j-th stage is applied as parallel data input to a multiplexer block in the (j+1)-th stage; and

a variable delay circuit connected to a data input terminal of each multiplexer block in one of the second to the n-th stages, the variable delay circuit delaying data input by a variable delay time.

2. The multiplexer of claim 1 further including:

means for monitoring data output from the data output terminal of the D flip-flop in the n-th stage; and

means for controlling the delay time of the variable delay circuit with a control signal in response to the monitoring.

3. The multiplexer of claim 2 wherein the variable delay circuit comprises:

a plurality of lines respectively comprising different numbers of buffers providing different delay times, the lines being arranged in parallel with each other; and

a selector for selecting one of the lines in response to the control signal supplied from the means for controlling the delay time, the selector being connected to the lines and to the means for controlling delay time.

4. The multiplexer of claim 2 wherein the variable delay circuit comprises at least a variable delay buffer connected to the means for controlling the delay time for varying the variable delay time in response to the control signal.

5. The multiplexer of claim 4 wherein the variable delay buffer comprises a source follower buffer including a current supply transistor in which the delay time is controlled by controlling a gate voltage of the current supply transistor with the control signal supplied from the means for controlling the delay time.

8. The multiplexer of claim 3 further including:

means for monitoring data output from the data output terminal of the multiplexer block in the n-th stage; and

means for controlling the delay time of the variable delay circuit with a control signal in response to the monitoring.

6. A multiplexer comprising:

an n-th stage as a final output stage (n=integer, 2≦

n);

j stages (j=integer, 1≦

j≦

n-1),

the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal,

a j-th stage including m^n-j-1 (m=integer, 2≦

m) multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, a multiplexer block in the j-th stage being connected to a multiplexer block in the (j+1)-th stage so that the serial data output from a multiplexer block in the j-th stage is applied as parallel data input to a multiplexer block in the (j+1)-th stage; and

a variable delay circuit connected to the clock input terminal of each multiplexer block in one of the first to the (n-1)th stages or to the clock input terminal of the D flip-flop in the n-th stage, the variable delay circuit delaying the clock input by a variable delay time.

7. A multiplexer comprising:

an n-th stage as a final stage (n=integer, 2≦

n);

h stages (h=integer, 1≦

h≦

n-1),

the n-th stage including a multiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving m (m=integer, 2≦

m) inputs of parallel data, and a data output terminal, the multiplexer block converting the parallel data into serial data in response to the first clock signal,

an h-th stage including m^n-h multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, and a multiplexer block in the h-th stage being connected to a multiplexer block in the (h+1)-th stage so that the serial data output from a multiplexer block in the h-th stage is applied as parallel data input to a multiplexer block in the (h+1)-th stage; and

a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages, the variable delay circuit delaying data input by a variable delay time.

9. A multiplexer comprising:

an n-th stage as a final stage (n=integer, 2≦

n);

h stages (h=integer, 1≦

h≦

n-1),

the n-th stage including a multiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving m (m=integer, 2≦

m) inputs of parallel data, and a data output terminal, the multiplexer block converting the parallel data into serial data in response to the first clock signal;

an h-th stage including m^n-h multiplexer blocks, each multiplexer block comprising a plurality of D flip-flops and having data input terminals for receiving m inputs of parallel data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each multiplexer block converting parallel data into serial data in response to the second clock signal, and a multiplexer block in the h-th stage being connected to a multiplexer block in the (h+1)-th stage so that the serial data output from a multiplexer block in the h-th stage is applied as parallel data input to a multiplexer block in the (h+1)-th stage; and

a variable delay circuit connected to a data input terminal of each multiplexer block in one of the first to the (n-1) stages or to the clock input terminal of the multiplexer block in the n-th stage, the variable delay circuit delaying the clock input by a variable delay time.

10. A demultiplexer comprising;

a first stage;

i stages (i=integer, 2≦

i≦

n (n=integer, 2≦

n),

the first stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal,

an i-th stage including m^i-2 (m=integer, 2≦

m) demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the i-th stage being connected to a demultiplexer block in the (i-1)-th stage so that parallel data outputs from a demultiplexer block in the (i-1)-th stage is input to each demultiplexer block in the i-th stage as serial data; and

a variable delay circuit connected to the data input terminal of each demultiplexer block in one of the second to the nth stages, the variable delay circuit delaying the data input by a variable delay time.

11. The demultiplexer of claim 10 further including:

means for monitoring data output from the data output terminals of the demultiplexer blocks in the n-th stage; and

means for controlling the delay time of the variable delay circuit with a control signal in response to the monitoring.

12. The multiplexer of claim 11 wherein the variable delay circuit comprises:

a plurality of lines respectively comprising different numbers of buffers providing different delay times, the lines being arranged in parallel with each other; and

a selector for selecting one of the lines in response to the control signal supplied from the means for controlling the delay time, the selector being connected to the lines and to the means for controlling delay time.

13. The multiplexer of claim 11 wherein the variable delay circuit comprises at least a variable delay buffer connected to the means for controlling the delay time for varying the variable delay time in response to the control signal.

14. The demultiplexer of claim 13 wherein the variable delay buffer comprises a source follower buffer including a current supply transistor in which the delay time is controlled by controlling a gate voltage of the current supply transistor with the control signal supplied from the means for controlling the delay time.

15. A demultiplexer comprising:

a first stage;

i stages (i=integer, 2≦

i≦

n (n=integer, 2≦

n)),

the first stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the serial data with the first clock signal,

an i-th stage including m^i-2 (m=integer, 2≦

m) demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the i-th stage being connected to a demultiplexer block in the (i-1)-th stage so that parallel data outputs from a demultiplexer block in the (i-1)-th stage is input to each demultiplexer block in the i-th stage as serial data; and

a variable delay circuit connected to the clock input terminal of each demultiplexer block in one of the second to the nth stages or to the clock input terminal of the D flip-flop in the first stage, the variable delay circuit delaying the clock input by a variable delay time.

16. A demultiplexer comprising:

a first stage;

k stages (k=integer, 2≦

k≦

n (n=integer, 2≦

n)),

the first stage including a demultiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the demultiplexer block converting the serial data into m (m=integer 2≦

m) parallel data outputs in response to the first clock signal,

a k-th stage including m^k-1 demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the k-th stage being connected to a demultiplexer block in a (k-1)-th stage so that parallel data output from a demultiplexer block in the (k-1)-th stage is input to each demultiplexer block in the k-th stage as the serial data; and

a variable delay circuit connected to the data input terminal of each demultiplexer block in one of the second to the nth stages, the variable delay circuit delaying the data input by a variable delay time.

17. The demultiplexer of claim 16 further including:

means for monitoring data output from the data output terminals of the demultiplexer blocks in the n-th stage; and

means for controlling the delay time of the variable delay circuit with a control signal in response to the result of the monitoring.

18. A demultiplexer comprising:

a first stage;

k stages (k=integer, 2≦

k≦

n (n=integer, 2≦

n)),

the first stage including a demultiplexer block comprising a plurality of D flip-flops and having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the demultiplexer block converting the serial data into m (m=integer, 2≦

m) parallel data outputs in response to the first clock signal;

a k-th stage including m^k-1 demultiplexer blocks, each demultiplexer block comprising a plurality of D flip-flops and having a data input terminal for receiving serial data and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, each demultiplexer block converting serial data into m parallel data outputs in response to the second clock signal, a demultiplexer block in the k-th stage being connected to a demultiplexer block in a (k-1)-th stage so that parallel data output from a demultiplexer block in the (k-1)-th stage is input to each demultiplexer block in the k-th stage as the serial data; and

a variable delay circuit connected to the clock input terminal of each demultiplexer block in any of the second to the nth stages or to the clock input terminal of the D flip-flop in the first stage, the variable delay circuit delaying the clock input by a variable delay time.