Apparatus for and method of speech digitizing

• US 5,727,023 A
• Filed: 09/14/1993
• Issued: 03/10/1998
• Est. Priority Date: 10/27/1992
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Dent, Paul W.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): WEBSTER, BRYAN E
• Application Number:
  US08/120,426
• Time in Patent Office: 1,638 Days
• Field of Search: 364/724, 341/126, 341/155, 341/159, 341/161, 341/164-168, 375/27, 375/28, 375/30, 375/32, 375/244, 375/247, 375/249, 375/251
• US Class Current: 375/244
• CPC Class Codes: H03C 1/542 comprising semiconductor devices with at least three electrodes
• CPC Class Codes: H03H 1/02 of RC networks, e.g. integrated networks
• CPC Class Codes: H03M 3/024 using syllabic companding, e.g. continuously variable slope delta modulation [CVSD]
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0014 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/0039 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 25/03834 using pulse shaping
• CPC Class Codes: H04L 27/2017 in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation H04L27/201 takes precedence
• CPC Class Codes: H04L 27/2064 using microwave technology

Abstract

A speech encoder converts analog speech signals into a stream of binary coded speech samples. A circuit for performing analog to digital conversion compares an input speech signal with a signal from a digital integrator. Based on the comparison a series of decisions are registered which indicate a step sign of the input signal. A syllabic filter generates a step magnitude according to the registered decisions. The step sign and step magnitude are combined providing a sign/magnitude representation of the input signal. When the sign/magnitude representation is integrated digitally in a decimation filter a digital representation of the analog signal is formed. A speech decoder, the antithesis of the encoder, converts binary coded speech samples into an analog waveform in a manner opposite to the A/D conversion method.

Claims

1. A circuit for converting an analog waveform signal to a digital waveform signal, said circuit comprising:

first integrator means for generating an integrated signal;

means for comparing said analog waveform signal with said integrated signal and for registering a series of increment/decrement values, one value per predetermined interval;

means for setting a step sign of said integrated signal based on a most recent of said registered increment/decrement values;

syllabic filter means for accumulating a series of registered increment/decrement values in a second, leaky digital integrator in order to select a step magnitude; and

decimation filter means for processing said step sign and said step magnitude to generate a sequence of binary coded digital signals representative of said analog waveform signal.

2. The circuit of claim 1 wherein said integrator means includes at least one programmable current source connected to one side of a capacitor, the other side of which is connected to a fixed potential.

3. The circuit of claim 2 wherein current magnitude of said at least one programmable current source is programmed according to said step magnitude desired.

4. The circuit of claim 2 wherein at least one of said at least one programmable current source is programmed according to a current pulse width.

5. The circuit of claim 4 wherein said current pulse width is programmed according to said step magnitude desired.

6. The circuit of claim 2 wherein current direction of said at least one programmable current source is programmed according to said step sign.

7. The circuit of claim 1 wherein said syllabic filter means includes:

means for successively storing said registered increment/decrement values as a bit sequence; and

logic means for performing logic operations on said bit sequence and for generating an accumulated value indicative of said step magnitude according to said logic operations.

8. The circuit of claim 1 wherein said decimation filter includes a leaky digital integrator for integrating said step sign and said step magnitude to obtain a numerical value and means for subtracting a fraction of said numerical value from a next numerical value at predetermined intervals.

9. The circuit of claim 8 wherein said step magnitude is added to or subtracted from said numerical value according to said step sign.

10. The circuit of claim 9 wherein said decimation filter includes means for summing said numerical value over a plurality of values and generating a sum at predetermined intervals, said sum digitally representing said analog waveform signal.

11. The circuit of claim 2 wherein said at least one programmable current source includes a first programmable source and a second programmable source, said step magnitude being a 12-bit binary coded value, said binary coded value controlling said first programmable current source according to a number of least significant bits and controlling said second programmable current source according to a number of most significant bits, a first current of said first programmable current source being added to a second current of said second programmable current source.

12. The circuit of claim 11 wherein said number of least significant bits and said number of most significant bits is four and said at least one programmable current source includes a third programmable current source controlled by four bits in said binary coded value between said most significant bits and said least significant bits, a third current of said third programmable current source being added to said first current and said second current.

13. The circuit of claim 12 wherein said first current, said second current and said third current are in the ratios 1:

16;

256.

14. An analog to digital conversion circuit comprising:

a comparator for registering a series of decisions at regular intervals;

an input for an analog signal connected by a series capacitor to a first input of said comparator, second input of said comparator being connected to a reference voltage source; and

at least one pulse width modulated current source controlled by the output of said comparator, the current output pulse from said current source also being connected to said first comparator input.

15. The circuit of claim 14 wherein said pulse width changes depending on said series of decisions.

16. The circuit of claim 15 further including an accumulator that is modified in step with control of said capacitor by said pulse width changes.

17. The circuit of claim 16 wherein said accumulator is leaky.

18. The circuit of claim 16 including means for adding N successive values of said accumulator producing a series of binary coded output values, one binary coded output value per N modification periods of said accumulator, said binary coded values representing said analog input signal.

19. The circuit of claim 15 wherein said series of decisions are output as a companded delta-modulation bit stream representative of said analog input signal.

20. The circuit of claim 19 wherein said bit stream includes a word synchronization strobe indicating location of a block of bits forming each binary coded output value.

21. A circuit for converting a plurality of binary coded numerical signal samples to an analog signal waveform, said circuit comprising:

means for interpolating between successive binary coded numerical signal samples to produce N interpolated samples for each binary coded numerical signal sample;

means for comparing said interpolated samples with values in a digital integrator and for registering a series of decisions;

means for modifying said digital integrator values according to said decisions by a step sign;

syllabic filter means for generating a step magnitude for modifying said digital integrator values depending on a successive number of said decisions;

leaky analog integrator means for receiving said step sign and said step magnitude and for generating an analog signal described numerically by said digital integrator values; and

means for filtering said analog signal to produce an analog waveform corresponding to said binary coded numerical signal samples.

22. The circuit of claim 21 wherein said syllabic filter means includes:

means for successively storing said series of decisions as a bit sequence; and

logic means for performing logic operations on said bit sequence and for generating an accumulated value indicative of said step magnitude according to said logic operations.

23. The circuit of claim 21 wherein said analog integrator means includes at least one programmable current source connected to a capacitor.

24. The circuit of claim 23 wherein current magnitude of said at least one programmable current source is programmed according to said step magnitude desired.

25. The circuit of claim 23 wherein at least one of said at least one programmable current source is programmed to produce a current pulse width.

26. The circuit of claim 25 wherein said current pulse width is programmed according to said step magnitude desired.

27. The circuit of claim 23 wherein current direction of said at least one programmable current source is programmed according to said step sign.

28. A digital-to-analog conversion circuit comprising:

means for receiving a companded delta-modulation bit stream;

syllabic filter means for generating a plurality of variable step magnitudes based on a successive number of bits in said bit stream;

at least two variable pulse width current sources controlled by separate digits of said variable step magnitudes;

integrator means for integrating current pulses from said at least two current sources to generate an analog output signal; and

means for filtering said analog output signal to produce an analog waveform corresponding to said bit stream.

29. The circuit of claim 28 wherein said integrator means includes connecting at least one of said pulse width modulated current sources to a capacitor.

30. A method of converting an analog waveform signal to a digital waveform signal, said method comprising the steps of:

generating an integrated signal by integrating a series of step inputs;

comparing said analog waveform signal with said integrated signal and registering a series of decisions, one decision per predetermined interval;

setting a step sign for said integrated signal based on a most recent of said registered decisions;

selecting a step magnitude based on said registered decisions; and

decimating said step sign and said step magnitude to generate a sequence of binary coded digital signals representative of said analog waveform signal dependent on all of said sequentially produced step magnitudes.

31. A method of converting a plurality of binary coded numerical signal samples to an analog signal waveform, said method comprising the steps of:

interpolating between successive binary coded numerical signal samples to produce N interpolated samples for each binary coded numerical signal sample;

comparing said interpolated samples with values in a digital integrator and registering a series of step sign decisions;

modifying said digital integrator values according to said decisions by a step sign and step magnitude;

generating a step magnitude for modifying said digital integrator values depending on a successive number of said decisions;

processing said step sign and said step magnitude and generating therefrom an analog signal described numerically by said digital integrator values; and

filtering said analog signal to produce an analog waveform corresponding to said binary coded numerical signal samples.

32. A circuit for converting a plurality of binary coded numerical signal samples to an analog signal waveform, said circuit comprising:

means for interpolating between successive binary coded numerical signal samples to produce N interpolated samples for each binary coded numerical signal sample;

means for comparing said interpolated samples with values in a digital integrator and for registering a series of decisions;

means for modifying said digital integrator values according to said decisions by a step sign;

syllabic filter means for accumulating said series of decisions in a leaky digital integrator in order to select a step magnitude; and

leaky analog integrator means for receiving said step sign and said step magnitude and for generating an analog signal described numerically by said digital integrator values; and

means for filtering said analog signal to produce an analog waveform corresponding to said binary coded numerical signal samples.