PSK signal demodulation method and apparatus

• US 5,727,027 A
• Filed: 12/17/1996
• Issued: 03/10/1998
• Est. Priority Date: 03/07/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tsuda, Hiroki
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GHAYOUR, MOHAMMAD H
• Application Number:
  US08/775,707
• Time in Patent Office: 448 Days
• Field of Search: 375/329, 375/324, 375/323, 375/326, 375/344, 375/371, 329/306, 455/119, 370/104.1
• US Class Current: 375/329
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier

Abstract

In a PSK signal demodulation method of demodulating a received signal by sampling processing, one sampling interval is time-divided. A received signal is detected in different carrier frequency offset ranges in the respective time-division intervals. Reception processing is continuously performed in only a time-division interval in which the received signal is detected after the received signal is detected, thereby synchronizing carrier phase. A PSK signal demodulation apparatus is also disclosed.

Claims

1. A PSK signal demodulation method of demodulating a received signal by sample processing, comprising the steps of:

time-dividing one sampling interval;

detecting a received signal in different carrier frequency offset ranges in the respective time-division intervals; and

continuously performing reception processing in only a time-division interval in which the received signal is detected after the received signal is detected, thereby synchronizing carrier phase on the basis of clock synchronizing of the sampling interval.

10. A PSK signal demodulation method of claim 1, wherein time-division between sampling intervals is performed up to signal detection.

2. A PSK signal demodulation method of demodulating a received signal by sampling processing, comprising the steps of:

time-dividing one sampling interval;

generating different frequency signals in the respective time-division intervals to frequency-convert the received signal;

detecting the received signal on the basis of a correlation between an envelope of a PSK signal after the frequency conversion and a reference clock synchronized with the sampling operation; and

continuously performing reception processing in only a time-division interval in which the received signal is detected after the received signal is detected, thereby synchronizing carrier phase.

3. A PSK signal demodulation method of demodulating a received signal by sampling processing, comprising the steps of:

time-dividing one sampling interval;

generating different frequency signals in the respective time-division intervals to frequency-convert the received signal;

detecting the received signal on the basis of a correlation between an envelope of a PSK signal after the frequency conversion and a reference clock synchronized with the sampling operation;

continuously performing reception processing in only a time-division interval in which the received signal is detected after the received signal is detected;

detecting a clock phase error on the basis of the correlation to output an optimum sampling signal by interpolation; and

synchronizing carrier phase by using the optimum sampling signal.

4. A PSK signal demodulation apparatus comprising:

an A/D converter for sampling a received signal;

a voltage-controlled oscillator for generating multiple different frequency signals;

an offset generating circuit for generating a frequency control signal in accordance with an address signal to output the frequency control signal to said voltage-controlled oscillator;

a frequency converter for receiving outputs from the A/D converter and the voltage-controlled oscillator;

a received signal detector for detecting a received signal on the basis of the interrelationship between an envelope of the PSK signal after frequency conversion and standard clock synchronizing of the sampling signal, and

an address control circuit for receiving the output from the received signal detector, supplying address signals to the offset generating circuit in accordance with reception in different carrier frequency offset ranges, and when detecting the received signal, continuously outputting a corresponding address signal after detection of the received signal.

5. An apparatus according to claim 4, further comprising a first memory unit for temporarily storing processing information of multiple different frequency signals generated by said voltage-controlled oscillator, said first memory unit performing read and write operations with respect to processing information for the frequency signals for said voltage-controlled oscillator in accordance with the address signals output from said address control circuit.

6. A PSK signal for demodulation apparatus comprising:

an A/D converter for sampling a received signal;

a voltage-controlled oscillator for generating multiple different frequency signals;

an offset generating circuit for generating a frequency control signal in accordance with an address signal to output the frequency control signal to said voltage-controlled oscillator;

a frequency converter for receiving outputs from said A/D converter and said voltage-controlled oscillator;

a received signal detector for detecting a received signal on the basis of the output from said frequency converter;

an address control circuit for receiving the output from said received signal detector, supplying address signals to said offset generating circuit in accordance with reception in different carrier frequency offset ranges, and when detecting the received signal, continuously outputting a corresponding address signal after detection of the received signal; and

a filter for Nyquist-band-limiting an output signal from said frequency converter, an envelope detector for detecting an envelope of an output from said filter, a reference clock generating circuit for generating a reference clock synchronized with the sampling operation, a correlator for calculating a correlation between the envelope and the reference clock, and an integrator for integrating an output from said correlator.

7. An apparatus according to claim 6, further comprising second and third memory units for temporarily storing processing information from said filter and said integrator, said second and third memory unit performing read and write operations with respect to the processing information for said filter and said integrator in accordance with the address signals output from said address control circuit.

8. An apparatus according to claim 6, further comprising an interpolation circuit for receiving an output from said filter and calculating an optimum sampling signal from a clock phase error based on an output from said correlator.

9. An apparatus according to claim 8, further comprising a carrier recovery circuit for receiving an output from said interpolation circuit, said carrier recovery circuit being started, when said received signal detector detects a received signal, to output an automatic frequency control signal from said voltage-controlled oscillator.