Method of using logical names in post-synthesis electronic design automation systems

• US 5,727,187 A
• Filed: 08/31/1995
• Issued: 03/10/1998
• Est. Priority Date: 08/31/1995
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Reindel, Harold E., Lemche, Carol L.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOPPNOW, MATTHEW CLAY
• Application Number:
  US08/521,697
• Time in Patent Office: 922 Days
• Field of Search: 395/500, 364/488-491, 364/578
• US Class Current: 716/102
• CPC Class Codes: G06T 1/00 General purpose image data processing

Abstract

A method used by an electronic design automation system for allowing the use of logical names from a register transfer level description of an integrated circuit design in timing notes and simulation tests written for timing analysis and simulation programs. A synthesis program generates a state map file containing an entry for the logical name for each state defined in the register transfer level description of the integrated circuit. The gate level name generated by the synthesis program corresponding to the logical state name is stored in the entry providing a one to one mapping of a logical state name to a gate level state name. The state map file is input to timing analysis and simulation programs wherein references to the logical state names in timing notes and simulation tests are translated to gate level state names before further processing.

Claims

1. In a system for designing a circuit, the system including a first level description of the circuit design, the first level description referencing logical state names for the circuit'"'"'s components and nets, a synthesis program taking as input the first level description and generating a second level description of the circuit design, the second level description referencing gate level state names for the circuit'"'"'s components and nets, and a post-synthesis program for analyzing the design of the circuit, the post-synthesis program for processing a control file which references logical state names and for further processing the second level description, a computer-implemented method of using logical state names in a post-synthesis program comprising the steps of:

(a) creating an electronic file for storing relationships between the logical state names specified in the first level description of the circuit design and the gate level state names specified in the second level description of the circuit design;

(b) creating an entry in said electronic file for a logical state name specified in the first level description of the circuit design;

(c) storing in said entry a gate level state name corresponding to said logical state name specified in the first level description;

(d) repeating steps (b) and (c) for all logical state names in the first level description;

(e) providing said electronic file to the post-synthesis program; and

(f) automatically translating the references to logical state names in the control file into corresponding gate level state names by searching said electronic file for each of said logical state names in the control file and returning a corresponding gate level state name to the post-synthesis program.

2. The computer-implemented method of claim 1, further comprising the step of repeating steps (a) through (e) each time the first level description is modified.

3. The computer-implemented method of claim 1, further comprising the step of sorting said electronic file before inputting said electronic file to the post-synthesis program.

4. In an electronic design automation system for designing an integrated circuit, the electronic design automation system including a register transfer level description of the integrated circuit design, the register transfer level description referencing logical names of state for the integrated circuit'"'"'s components, a synthesis program taking as input the register transfer level description and generating a gate level description of the integrated circuit design, the gate level description referencing gate level state names for the integrated circuit'"'"'s components, a post-synthesis timing verification program for analyzing the timing of the integrated circuit design, the post-synthesis timing verification program taking as input a timing notes file and the gate level description, a computer-implemented method of using logical state names in a post-synthesis timing verification program comprising the steps of:

(a) creating an electronic file for storing relationships between the logical names of states specified in the register transfer level description of the integrated circuit design and the gate level names of states specified in the gate level description of the integrated circuit design;

(b) creating an entry in said electronic file for a logical state name specified in the register transfer level description of the integrated circuit design;

(c) storing a gate level state name specified in the gate level description of the integrated circuit design corresponding to said logical state name specified in the register transfer level description into said entry;

(d) repeating steps (b) and (c) for all logical state names in the register transfer level description;

(e) inputting said electronic file to the post-synthesis timing verification program; and

(f) automatically translating references to logical state names in the timing notes file into corresponding gate level state names by searching said electronic file for said entries representing said logical state names and returning said gate level state names stored in said entries to the post-synthesis timing verification program.

5. The computer-implemented method of claim 4, further comprising the step of sorting said electronic file before inputting said electronic file to the post-synthesis timing verification program.

8. The computer-implemented method of claim 4 or claim 6, further comprising the step of repeating steps (a) through (e) each time the register transfer level description is modified.

6. In an electronic design automation system for designing an integrated circuit, the electronic design automation system including a register transfer level description of the integrated circuit design, the register transfer level description referencing logical state names for the integrated circuit'"'"'s components and nets, the electronic design automation system further including a synthesis program taking as input the register transfer level description and generating a gate level description of the integrated circuit design, the gate level description referencing gate level state names for the integrated circuit'"'"'s components and nets, the electronic design automation system still further including a post-synthesis simulation program for simulating the performance of the integrated circuit design, the post-synthesis simulation program taking as input a simulation test file and the gate level description, a computer-implemented method of using logical state names in a post-synthesis simulation program comprising the steps of:

(a) creating an electronic file for storing relationships between the logical state names specified in the register transfer level description of the integrated circuit design and the gate level state names specified in the gate level description of the integrated circuit design;

(b) creating an entry in said electronic file for a logical state name specified in the register transfer level description of the integrated circuit design;

(c) storing a gate level state name specified in the gate level description of the integrated circuit design corresponding to said logical state name specified in the register transfer level description into said entry;

(d) repeating steps (b) and (c) for all logical state names in the register transfer level description;

(e) inputting said electronic file to the post-synthesis simulation program; and

(f) automatically translating references to logical state names in the simulation test file into corresponding gate level state names by searching said electronic file for ones of said entries representing said references to logical state names in the simulation test file and returning said gate level state names stored in said ones of said entries to the post-synthesis simulation program.

7. The computer-implemented method of claim 6, further comprising the step of sorting said electronic file before providing said electronic file to the post-synthesis simulation program.

9. An electronic design automation system for designing and testing an application specific integrated circuit (ASIC), including a design capture sub-system for generating a register transfer level description of the ASIC design based on a circuit designer'"'"'s requests, the register transfer level description referencing logical names of states for the ASIC'"'"'s components and nets, the electronic design automation system further including a synthesis sub-system for taking as input the register transfer level description and generating a gate level description of the ASIC design, the gate level description referencing gate level names of states for the ASIC'"'"'s components, the electronic design automation system further including a post-synthesis timing sub-system for analyzing the timing of the ASIC design, the post-synthesis timing sub-system taking as input a timing notes file specified using gate level names of states and the gate level description, and the electronic design automation system still further including a post-synthesis simulation sub-system for simulating the performance of the ASIC, the post-synthesis simulation sub-system taking as input a simulation test file specified using gate level names of states and the gate level description, the electronic design automation system comprising:

a processor;

a storage device coupled to said processor;

a state map electronic file resident in said storage device for storing relationships between logical names of states specified in the register transfer level description of the ASIC design and the gate level names of states specified in the gate level description of the ASIC design; and

software means operative on said processor for;

(a) creating entries in said state map electronic file, each of said entries for storing a logical name of a state specified in the register transfer level description of the ASIC design;

(b) storing into each of said entries a gate level name of a state specified in the gate level description of the ASIC design and corresponding to said logical name of a state specified in said entry;

(c) providing said state map electronic file to the post-synthesis timing sub-system and the post-synthesis simulation sub-system; and

(d) translating references to logical names of states in the timing notes file and the simulation test file into corresponding gate level names of states by searching said state map electronic file for ones of said entries representing logical names of states contained in said references and returning gate level names of state stored in said ones of said entries to the post-synthesis timing sub-system and the post-synthesis simulation sub-system.

10. A system for designing a circuit, the system including a first level description of the circuit design, the first level description referencing logical state names for the circuit'"'"'s components and nets, a synthesis program taking as input the first level description and generating a second level description of the circuit design, the second level description referencing gate level state names for the circuit'"'"'s components and nets, and a post-synthesis program for analyzing the design of the circuit, the post-synthesis program taking as input a control file and the second level description, the system comprising:

means for creating an electronic file for storing relationships between the logical state names specified in the first level description of the circuit design and the gate level state names specified in the second level description of the circuit design;

means for creating an entry in said electronic file for each logical state name specified in the first level description of the circuit design;

means for storing a gate level state name specified in the second level description of the circuit design corresponding to a logical state name specified in the first level description into said entry;

means for sorting said electronic file according to predetermined criteria;

means for providing said electronic file to the post-synthesis program; and

means for automatically translating references made by the control file to logical state names into corresponding gate level state names by searching said electronic file for ones of said entries representing said references made by the control file to logical state names and returning from said ones of said entries said gate level state names to be provided to the post-synthesis program.

11. An electronic design automation system for designing an integrated circuit, the electronic design automation system including a register transfer level description of the integrated circuit design, the register transfer level description referencing logical state names for the integrated circuit'"'"'s components, the electronic design automation system further including a synthesis program taking as input the register transfer level description and generating a gate level description of the integrated circuit design, the gate level description referencing gate level state names for the integrated circuit'"'"'s components wherein predetermined ones of the gate level state names correspond to corresponding ones of the logical state names, the electronic design automation system further including a post-synthesis timing verification program for analyzing the timing of the integrated circuit design, the post-synthesis timing verification program taking as input a timing notes file and the gate level description, the electronic design automation system comprising:

means for creating an electronic file for storing relationships between the logical state names specified in the register transfer level description of the integrated circuit design and the gate level state names specified in the gate level description of the integrated circuit design;

means for creating an entry in said electronic file for each logical state name specified in the register transfer level description of the integrated circuit design;

means for storing a gate level state name specified in the gate level description of the integrated circuit design into an entry storing a corresponding logical state name;

means for sorting said electronic file according to predetermined criteria;

means for inputting said electronic file to the post-synthesis timing verification program; and

means for automatically translating references to logical state names in the timing notes file into corresponding gate level state names by searching said electronic file for entries representing said references to logical state names in the timing notes file and returning to the post-synthesis timing verification program said gate level state names stored in said entries representing said references.

12. An electronic design automation system for designing an integrated circuit, the electronic design automation system including a register transfer level description of the integrated circuit design, the register transfer level description referencing logical state names for the integrated circuit'"'"'s components and nets, the electronic design automation system including a synthesis program taking as input the register transfer level description and generating a gate level description of the integrated circuit design, the gate level description referencing gate level state names for the integrated circuit'"'"'s components and nets, wherein each of said gate level state names corresponds to a corresponding one of said logical state names, and the electronic design automation system further including a post-synthesis simulation program for simulating the performance of the integrated circuit design, the post-synthesis simulation program taking as input a simulation test file and the gate level description, the electronic design automation system comprising:

means for creating an electronic file for storing relationships between the logical state names specified in the register transfer level description of the integrated circuit design and the gate level state names specified in the gate level description of the integrated circuit design;

means for creating an entry in said electronic file for each logical state name specified in the register transfer level description, each said entry for storing a different one of the logical state names included in the integrated circuit design;

means for storing a gate level state name specified in the gate level description of the integrated circuit design into an entry for the corresponding logical state name;

means for sorting said entries of said electronic file according to predetermined criteria;

means for providing said electronic file to the post-synthesis simulation program; and

means for automatically translating references to logical state names in the simulation file into corresponding gate level state names by searching said electronic file for selected ones of said entries that store logical state names referenced in the simulation file and returning gate level state names stored in said selected ones of said entries to the post-synthesis simulation program.

13. An electronic design automation system for designing an application specific integrated circuit (ASIC), the electronic design automation system including a design capture program for generating a register transfer level description of the ASIC design, the register transfer level description referencing logical state names for the ASIC'"'"'s components, the electronic design automation system further including a synthesis program taking as input the register transfer level description and generating a gate level description of the ASIC design, the gate level description referencing gate level state names for the integrated circuit'"'"'s components, the electronic design automation system further including a post-synthesis timing program for analyzing the timing of the ASIC design, the post-synthesis timing program taking as input a timing notes file and the gate level description, and a post-synthesis simulation program for simulating the performance of the ASIC, the post-synthesis simulation program taking as input a simulation test file and the gate level description, the electronic design automation system comprising:

means for creating an electronic file for storing relationships between the logical state names specified in the register transfer level description of the ASIC design and the gate level state names specified in the gate level description of the ASIC design;

means for creating an entry in said electronic file for each logical state name specified in the register transfer level description of the ASIC design;

means for storing a gate level state name specified in the gate level description of the ASIC design corresponding to a logical state name specified in the register transfer level description into said entry;

means for sorting said electronic file according to predetermined criteria;

means for inputting said electronic file to the post-synthesis timing program and the post-synthesis simulation program; and

means for automatically translating references to logical state names in the timing notes file and the simulation test file into corresponding gate level state names by searching said electronic file for said entries representing said logical state names and returning said gate level state names stored in said entries.