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Method of using logical names in post-synthesis electronic design automation systems

  • US 5,727,187 A
  • Filed: 08/31/1995
  • Issued: 03/10/1998
  • Est. Priority Date: 08/31/1995
  • Status: Expired due to Fees
First Claim
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1. In a system for designing a circuit, the system including a first level description of the circuit design, the first level description referencing logical state names for the circuit'"'"'s components and nets, a synthesis program taking as input the first level description and generating a second level description of the circuit design, the second level description referencing gate level state names for the circuit'"'"'s components and nets, and a post-synthesis program for analyzing the design of the circuit, the post-synthesis program for processing a control file which references logical state names and for further processing the second level description, a computer-implemented method of using logical state names in a post-synthesis program comprising the steps of:

  • (a) creating an electronic file for storing relationships between the logical state names specified in the first level description of the circuit design and the gate level state names specified in the second level description of the circuit design;

    (b) creating an entry in said electronic file for a logical state name specified in the first level description of the circuit design;

    (c) storing in said entry a gate level state name corresponding to said logical state name specified in the first level description;

    (d) repeating steps (b) and (c) for all logical state names in the first level description;

    (e) providing said electronic file to the post-synthesis program; and

    (f) automatically translating the references to logical state names in the control file into corresponding gate level state names by searching said electronic file for each of said logical state names in the control file and returning a corresponding gate level state name to the post-synthesis program.

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