Method of making a multiple transistor integrated circuit with thick copper interconnect

• US 5,728,594 A
• Filed: 06/07/1995
• Issued: 03/17/1998
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Efland, Taylor R., Cotton, David, Skelton, Dale J.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/474,621
• Time in Patent Office: 1,014 Days
• Field of Search: 437/40 DM, 437/41 DM, 437/44, 437/56, 257/335-339, 257/758, 257/773, 257/207, 257/211, 257/762
• US Class Current: 438/128
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.

Claims

1. A method of fabricating a multiple transistor integrated circuit with a thick metal interconnect structure, comprising the steps of:

providing a plurality of gate bond pads, each for receiving a gate input to a respective LDMOS transistor;

providing a plurality of source bond pads, each for receiving a source input to a respective LDMOS transistor, all coupled together and to a common source buss;

providing a plurality of columns of multiple rows of diffusion regions, said diffusion regions alternating and being of a first and a second conductivity type;

providing first level metal layers placed over and electrically contacting each of said diffusion regions, said first level metal layers forming source stripes and drain stripes;

providing a plurality of columnar second level metal source busses, each coupled to said common source bus and each partially overlying a respective one of said plurality of columns of multiple rows of diffusions, each columnar second level metal source bus being coupled to selected ones of said source stripes;

providing a plurality of columnar second level metal drain busses, each coupled to a respective one of said drain bond pads, each partially overlying a respective one of said plurality of columns of multiple rows of diffusions and each being spaced apart from said plurality of columnar second level source busses, said source and drain busses being alternating columnar busses;

providing a plurality of third level thick metal source shorting busses, each associated with and partially overlying a respective one of said source busses, said third level thick metal source shorting busses not overlying said source bond pads; and

providing a plurality of third level thick metal drain shorting busses, each associated with and partially overlying a respective one of said drain busses;

the third level thick metal source and drain shorting busses being in electrical contact with said source and drain busses and lowering the on resistance of the LDMOS transistors on the integrated circuit.