Sense amplifier having capacitively coupled input for offset compensation

• US 5,729,492 A
• Filed: 04/26/1996
• Issued: 03/17/1998
• Est. Priority Date: 04/28/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Campardo, Giovanni
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/639,192
• Time in Patent Office: 690 Days
• Field of Search: 365/185.21, 365/185.2, 365/233.5, 365/185.3, 365/189.07, 365/185.12, 365/185.13, 365/185.33, 365/190, 365/207, 365/208, 365/210
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A sense amplifier circuit for a semiconductor memory device comprises a first current/voltage converter for convening a current of a memory cell to be read into a voltage signal, a second current/voltage converter for converting a reference current into a reference voltage signal, and a voltage comparator for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises a capacitive decoupler for decoupling the voltage signal from the comparator, and circuitry for providing the capacitive decoupler with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

Claims

1. A sense amplifier circuit for reading one of a plurality of memory cells that are coupled to a bit line, the circuit comprising:

a supply terminal;

a reference memory cell;

a comparator having first and second input terminals and having an output terminal that provides a read signal;

a first load device having a first terminal coupled to said supply terminal and having a second terminal coupled to said bit line;

a second load device having a first terminal coupled to said supply terminal and having a second terminal coupled to said reference memory cell and to said second input terminal of said comparator;

a first capacitive component having a first terminal coupled to said second terminal of said first load device and having a second terminal coupled to said first input terminal of said comparator; and

a first switch having a control terminal, a first terminal coupled to said supply terminal, and a second terminal coupled to said second terminal of said first capacitive component, said first switch operable to allow an offset-compensation charging current to flow through said first capacitive component to said bit line.

2. The sense amplifier circuit of claim 1 further comprising a voltage regulator coupled between said first load device and said bit line, said voltage regulator having a first terminal coupled to said second terminal of said first load device and having a second terminal coupled to said bit line.

3. The sense amplifier circuit of claim 1 further comprising:

a second capacitive component having a first terminal coupled to said reference memory cell and a second terminal coupled to said second input terminal of said comparator;

the control terminal of said first switch coupled to receive a first control signal;

a second switch having a first switch terminal coupled to said supply terminal, a second switch terminal coupled to said second terminal of said second capacitive component, and a control terminal coupled to receive a second control signal;

a first voltage regulator coupled between said first load device and said bit line, said first voltage regulator having a first terminal coupled to said second terminal of said first load device and having a second terminal coupled to said bit line; and

a second voltage regulator coupled between said second load device and said reference memory cell, said second voltage regulator having a first terminal coupled to said second terminal of said second load device and having a second terminal coupled to said reference memory cell.

4. The sense amplifier circuit of claim 3 wherein said first control signal equals said second control signal.

5. The sense amplifier circuit of claim 4, further comprising an address transition detect circuit having a plurality of input terminals that are each coupled to receive a bit of an address signal and having an output terminal that is coupled to said control terminals of said first and second switches, said address transition detect circuit providing an address transition detect signal as said first and second control signals.

6. The sense amplifier circuit of claim 3, further comprising an address transition detect circuit having a plurality of input terminals that are each coupled to receive a bit of an address signal, said address transition detect circuit having first and second output terminals that are respectively coupled to said control terminals of said first and second switches and that respectively provide first and second address transition detect signals as said first and second control signals.

7. The sense amplifier circuit of claim 3 wherein said first control signal is delayed with respect to said second control signal.

8. A method for reading data stored in a memory cell of a plurality of memory cells that are coupled to a bit line, the method comprising:

before reading said memory cell, storing an offset-compensation signal that compensates for an offset signal on said bit line;

while reading said memory cell, combining said stored offset-compensation signal with a signal on said bit line to obtain a read signal from said memory cell; and

comparing said read signal with a reference signal to generate a data signal that identifies said data stored in said memory cell.

9. The method of claim 8 wherein said storing comprises storing in a capacitive element an offset-compensation voltage that is produced by an offset current generated on said bit line by a depleted one of said memory cells.

10. The method of claim 8 wherein:

said storing includes storing in a capacitive element an offset-compensation voltage that is produced by an offset current generated on said bit line by a depleted one of said memory cells; and

said combining includes adding said stored offset-compensation voltage to a voltage on said bit line to obtain a read voltage generated by said memory_ cell.

11. Sense amplifier circuit for a semiconductor memory device, comprising first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage signal, and voltage comparator means for comparing said voltage signal with said reference voltage signal, characterized in that said sense amplifier circuit comprises capacitive decoupling means for decoupling said voltage signal from said comparator means, and means for providing said capacitive decoupling means with an electric charge suitable for compensating an offset voltage introduced in said voltage signal by an offset current superimposed on the current of the memory cell to be read.

12. Sense amplifier circuit according to claim 11, characterized in that said offset current is a current sunk by at least one depleted memory cell connected in parallel to the memory cell to be read.

13. Sense amplifier circuit according to claim 11, characterized in that said first current/voltage conversion means comprise a first current/voltage conversion branch connected in series between a power supply and the memory cell to be read, said voltage comparator means comprises a comparator with a first input coupled to an output of said first conversion branch, and in that said capacitive decoupling means comprise a decoupling capacitor connected between said first input of the comparator and said output of said first conversion branch.

14. Sense amplifier circuit according to claim 13, characterized in that said means for providing the capacitive decoupling means with an electric charge comprise transistor means connected between the first input of the comparator and the power supply and operable to electrically connect said capacitor to the power supply.

15. Sense amplifier circuit according to claim 14, characterized in that said second current/voltage conversion means comprise a second current/voltage conversion branch connected in series between the power supply and current generator means generating said reference current, the second conversion branch having an output coupled to a second input of the comparator.

16. Sense amplifier circuit according to claim 15, characterized in that said current generator means comprise a reference memory cell identical to the memory cell to be read and having a predetermined threshold voltage.

17. Sense amplifier circuit according to claim 15, characterized by comprising a second decoupling capacitor connected between said output of the second conversion branch and the second input of the comparator, and by comprising second transistor means connected between the second input of the comparator and the power supply and operable to electrically connect the second decoupling capacitor to the power supply.

18. Sense amplifier circuit according to claim 17, said semiconductor memory device comprising a matrix of memory cells located at intersection of rows and columns of the matrix, column selection means for electrically coupling one of a group of said columns to said first current/voltage conversion branch, address decoding means for generating column selection signals for driving said column selection means and row selection signals for selecting one of said rows in response to external address signals of the memory device, characterized in that said semiconductor memory device comprises address transition detection means for temporarily activating said transistor means, in response to a change in the external address signals, for a predetermined time between the activation of the column selection signals and the activation of the row selection signals.