Address transition detection on a synchronous design

• US 5,729,503 A
• Filed: 07/24/1995
• Issued: 03/17/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/506,438
• Time in Patent Office: 967 Days
• Field of Search: 365/233.5, 365/230.08, 365/189.05, 365/202
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit. The address transition detection circuit generates an equilibration control signal between memory access cycles.

Claims

1. A circuit comprising:

an address buffer providing a first address;

an input adapted to receive an access cycle strobe signal;

a memory array;

an address generator coupled to said address buffer and to said input, said address generator adapted to provide a series of addresses in response to receipt of the first address and receipt of the access cycle strobe signal; and

an address transition detection circuit coupled to said address buffer and to said address generator, said address transition detection circuit having an output coupled to said memory array, providing a first equilibration signal to said memory array in response to the first address in a first mode of operation, and said address transition detection circuit providing a second equilibration signal to said memory array in response to each subsequent address of the series of addresses in a second mode of operation.

2. The circuit of claim 1 further comprising:

a mode select circuit coupled to said address generator.

3. The circuit of claim 1 wherein said memory array comprises a plurality of dynamic random access memory elements.

4. The circuit of claim 1 further comprising:

a pair of complimentary data lines coupled to said memory array; and

an equilibration circuit coupled to said complimentary data lines, responsive to the first or second equilibration signal to equilibrate said complimentary data lines.

5. A circuit comprising:

a memory array comprising a plurality of rows and a plurality of columns;

a column address generator, operable in a burst mode and a page mode, coupled to said memory array;

a mode select circuit coupled to said column address generator to select the burst mode or the page mode;

an address transition detection circuit coupled to said column address generator;

a pair of complimentary data lines coupled to said memory array; and

an equilibration circuit coupled to said complimentary data lines and to said address transition detection circuit.

6. A circuit comprising:

an address generator responsive to a first polarity of transitions of a control signal to provide a series of addresses;

an address latch responsive to a second polarity of transitions of the control signal to latch each of the series of addresses; and

an address transition detection circuit responsive to the latched addresses, said address transition detection circuit providing an equilibration control signal.

7. A method of operating a memory device having an address generation circuit, comprising steps of:

receiving an address from a source external to the memory device;

latching the address;

generating a next address in the address generation circuit;

latching the next address;

detecting a difference between the address and the next address; and

generating an equilibration signal in response to said step of detecting a difference.

8. A method of supplying data to a microprocessor comprising steps of:

addressing a memory circuit with an address from the microprocessor;

latching the address within the memory circuit;

generating a next address within the memory circuit;

detecting a difference between the address and the next address;

generating an equilibration signal within the memory circuit in response to said step of detecting a difference;

supplying data to the microprocessor from the address of the memory circuit; and

supplying data to the microprocessor from the next address of the memory circuit.