Semiconductor integrated circuit with a testable block

• US 5,729,553 A
• Filed: 07/19/1996
• Issued: 03/17/1998
• Est. Priority Date: 08/29/1994
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Motohara, Akira
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Tu, Trinh L.
• Application Number:
  US08/684,066
• Time in Patent Office: 606 Days
• Field of Search: 371/22.3, 371/22.5, 371/22.6, 371/22.1, 371/25.1, 371/67.1, 395/183.06
• US Class Current: 714/733
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

Claims

1. A semiconductor integrated circuit comprising a first block, a second block and a third block that are cascaded to one another and a test unit for testing the first, second and third blocks,

wherein the test unit includes:

a first multiplexer for selecting one of a test input signal supplied from an outside of the semiconductor integrated circuit and a part of an output signal of the second block, and supplying the selected signal to the third block;

a second multiplexer for selecting one of the signal selected by the first multiplexer and a part of an output signal of the first block;

a first control register for latching the signal selected by the second multiplexer synchronously with a clock signal and supplying the latched signal to the second block;

a third multiplexer for selecting one of the signal latched by the first control register and another part of the output signal of the second block, and supplying the selected signal to the third block;

a fourth multiplexer for selecting one of the signal selected by the third multiplexer and another part of the output signal of the first block; and

a second control register for latching the signal selected by the fourth multiplexer synchronously with the clock signal and supplying the latched signal to the second block.