Signal processor with improved efficiency

• US 5,729,577 A
• Filed: 05/21/1996
• Issued: 03/17/1998
• Est. Priority Date: 05/21/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Chen, Weizhong
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/646,804
• Time in Patent Office: 665 Days
• Field of Search: 375/272, 375/334, 375/342, 375/349, 329/300, 370/210, 455/205
• US Class Current: 375/334
• CPC Class Codes: H04L 1/16 in which the return channel carries supervisory signals, e.g. repetition request signals
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0046 Open loops
• CPC Class Codes: H04L 2027/0093 Intermittant signals
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier
• CPC Class Codes: H04L 27/3854 using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

A signal processor arranged and constructed to provide a discrete time Fourier transform (DTFT) corresponding to a sequence of samples, including a current, preferably, last sample, of a signal, the signal processor including a recursive structure (303), coupled to the signal and operating on the sequence of samples, for providing an output (309) and a first previous output (310), the output proportional to a combination of the current sample of the signal, and the first previous output weighted by a sinusoidal function, less a second previous output (316), the sinusoidal function having an argument corresponding to an arbitrary frequency, and a combiner (330) coupled to the output and the first previous output for providing a DTFT signal proportional to a DTFT evaluated at the arbitrary frequency for the sequence of samples.

Claims

1. A signal processor arranged and constructed to provide a discrete time Fourier transform (DTFT) corresponding to a sequence of samples, including a current sample, of a signal, the signal processor comprising in combination;

a recursive structure, coupled to the signal and operating on the sequence of samples, for providing an output and a first previous output, said output proportional to a combination of the current sample of the signal and the first previous output weighted by a sinusoidal function, less a second previous output, said sinusoidal function having an argument corresponding to an arbitrary frequency, and

a combiner coupled to said output and said first previous output for providing a DTFT signal proportional to a DTFT evaluated at said arbitrary frequency for said sequence of samples.

2. The signal processor of claim 1 where said combiner further provides said DTFT signal as a combination of said output and said first previous output weighted in proportion to said sinusoidal function.

3. The signal processor of claim 1 further including a signal conditioner operating to provide said sequence of samples so as to limit the magnitude of said output.

4. The signal processor of claim 3 wherein said conditioner phase shifts each sample of an input signal to provide said sequence of samples.

5. The signal processor of claim 1 wherein said sinusoidal function is 2cosω

, where ω

is a normalized frequency equal to 2π

times said arbitrary frequency divided by a sampling frequency.

6. The signal processor of claim 1 wherein said sequence of samples are complex samples and said DTFT signal is a complex value.

7. The signal processor of claim 1 wherein said recursive structure and said combiner are implemented in a digital signal processor.

8. The signal processor of claim 1 wherein said recursive structure and said combiner are implemented as an integrated circuit.

9. A symbol detector arranged and constructed to select a symbol encoded as frequency shift keyed (FSK) modulation from a sequence of samples, including a current sample, of a signal, the symbol detector comprising in combination;

a recursive structure, coupled to the signal and operating on the sequence of samples, for providing an output and a first previous output, said output proportional to a combination of the current sample of the signal and the first previous output weighted by a sinusoidal function, less a second previous output, said sinusoidal function having an argument corresponding to a frequency representative of the symbol, and

a combiner coupled to said output and said first previous output for providing a DTFT signal proportional to a DTFT evaluated at said frequency representative of the symbol for said sequence of samples.

10. The symbol detector of claim 9 where said combiner further provides said DTFT signal as a combination of said output and said first previous output weighted in proportion to said sinusoidal function.

11. The symbol detector of claim 9 further including a signal conditioner operating to provide said sequence of samples so as to limit the magnitude of said output.

12. The symbol detector of claim 11 wherein said conditioner phase shifts each sample of an input signal to provide said sequence of samples.

13. The symbol detector of claim 9 wherein said sinusoidal function is 2cosω

, where ω

is a normalized frequency equal to 2π

times said frequency corresponding to the symbol divided by a sampling frequency.

14. The symbol detector of claim 9 wherein said sequence of samples are complex samples and said DTFT signal is a complex value.

15. The symbol detector of claim 9 wherein said recursive structure and said combiner are implemented in a digital signal processor.

16. The symbol detector of claim 9 wherein said recursive structure and said combiner are implemented as an integrated circuit.

17. The symbol detector of claim 9 further including a magnitude selector coupled to said combiner and operating to form a magnitude of said DTFT signal, said recursive structure and said combiner further operating to form a second DTFT signal for a second frequency corresponding to a second symbol, said magnitude selector further forming a second magnitude of said second DTFT signal and selecting the symbol when said magnitude is larger than said second magnitude.