Semiconductor integrated circuit and communication control apparatus

• US 5,729,722 A
• Filed: 01/26/1996
• Issued: 03/17/1998
• Est. Priority Date: 01/27/1995
• Status: Expired due to Term

• Current Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Original Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Inventors: Matsumoto, Manabu
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/592,533
• Time in Patent Office: 781 Days
• Field of Search: 395/560, 395/750, 395/879, 395/185.08
• US Class Current: 713/601
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor integrated circuit, which can precisely measure the sleep time of a CPU by using a built-in oscillation circuit which does not utilize an oscillator to automatically activate the CPU, is disclosed. A communication control part of a responder mounted on a vehicle, which composes a toll road charging system, is composed of an LSI having a built-in CPU with a sleep function for automatically stopping operation clocks. The CPU is held in the sleep state for a certain time period from the time when the responder completes data communications with a ground station until the time when the responder exits the communication area of the ground station. The sleep time is measured by having a dividing counter downcount oscillation signals from a CR oscillation circuit built in the LSI. However, as the oscillation frequency of the CR oscillation circuit varies according to the operational environment, such as temperature, the CPU obtains the frequency error of the second clock pulses and correct the count value for sleep time measurement based on the reference clock pulses from a quartz oscillator, which becomes the operation clocks of its own, immediately before entering the sleep state.

Claims

1. A semiconductor integrated circuit comprising:

a CPU having a control program which causes said CPU to;

process data using reference clock pulses from an externally connected oscillator,

automatically cut off said reference clock pulses to said CPU when a specified condition is satisfied during the performance of said processing so that said CPU enters a sleep state, and

resume said process by applying said reference clock pulses to said CPU upon receiving a start signal so that said CPU exits said sleep state; and

a timer circuit, coupled to said CPU comprising;

an oscillation circuit composed of at least a capacity element, a resistance element and a semiconductor element, said oscillation circuit generating second clock pulses without using an externally connected oscillator; and

sleep time determining means for counting said second clock pulses from a start count value, and generating said start signal when a count value reaches a specified value;

wherein said CPU includes sleep time calibrating means for correcting said start count value before said CPU enters said sleep state based on a time error contained in said second clock pulses with respect to said reference clock pulses or reference signals externally inputted at a specified time interval.

2. A semiconductor integrated circuit according to claim 1, wherein said sleep time calibrating means comprises:

calculating means for counting said second clock pulses upon a receipt of a first reference signal of said reference signals, and for calculating said time error of said second clock pulses based on said count value of said second clock pulses and said specified time interval of said reference signals; and

correcting means for correcting said start count value based on said time error of said second clock pulses calculated by said calculating means.

3. A semiconductor integrated circuit according to claim 1, wherein:

said semiconductor integrated circuit is a communication controlling circuit comprising a mobile communication apparatus together with a communication circuit for performing radio communication with a ground station through an antenna and a communication start determining circuit for determining upon a receipt of specified electric waves from said ground station through said antenna that said apparatus has entered an area where communications with said ground station are possible and outputs communication start signals; and

said CPU performs a specified communication processing, which is transmitting and receiving data to and from said ground station through said communication circuit upon the output of said communication start signals from said communication start determination circuit, and determines that said specified condition for entering said sleep state have been satisfied upon the completion of said communication processing.

4. A semiconductor integrated circuit according to claim 1, further comprising:

reference time determining means for counting said reference clock pulses and for generating a reference timing signal when said reference time determining means counts a second calibration value of said reference pulses;

wherein said sleep time calibrating means comprises;

calculating means for setting said reference time determining means with said second calibration value and said sleep time determining means with a first calibration value, then concurrently operating said reference time determining means and said sleep time determining means, and calculating said time error contained in said second clock pulses based on the number of said reference timing signals and said start signals from said respective determining means; and

correcting means for correcting said start count value based on said time error of said second clock pulses calculated by said calculating means.

5. A semiconductor integrated circuit according to claim 4 wherein:

said CPU performs calculations of said calculating means and said correcting means after said specified condition for entering said sleep state has been satisfied, and

said CPU activates the sleep time determining means of said timer circuit after the completion of said calculations of said calculating means and correcting means, and then enters said sleep state.

13. A communication control apparatus according to claim 1, wherein the sleep time calibrating means comprises:

calculating means for counting the clock pulses by the timer means from the receipt of a first reference signal of said reference signals, and for calculating a correction coefficient based on the counted clock pulses by the timer means and a time interval from a timing of the first reference signal to a timing of the subsequent reference signal; and

correcting means for correcting the clock count value for use in the determination of the sleep time by the timer means based on the correction coefficient calculated by the calculating means.

14. A communication control apparatus according to claim 1, wherein the CPU enters a resumption enable state when the sleep time counted by the timer means reaches a specified time and resumes the processing operation in the resumption enable state when the communication circuit receives the communication signals.

15. A communication control apparatus according to claim 14, wherein the CPU resumes the proceeding operation when a signal level of the communication signals received by the communication circuit becomes equivalent to or higher then a specified signal level.

16. A communication control apparatus according to claim 1, further comprising:

reference time determining means for counting the reference clock pulses, and determining when a reference count value of the reference clock pulses reaches a reference calibration value;

wherein the sleep time calibrating means comprises;

calculating means for counting the clock pulses generated by the timer means to determine when the clock count value reaches a clock calibration value, and calculating a correction coefficient based on the relationship between when the reference count value reached the reference calibration value and when the clock count value reached the clock calibration value; and

correcting means for correcting the clock count value for use in the determination of the sleep time by the timer means based on the correction coefficient calculated by the calculating means.

17. A communication control apparatus according to claim 16, wherein:

the CPU performs calculation processing operations of the calculating means and the correcting means after the condition for entering the sleep state has been satisfied, and

the CPU starts the counting of the sleep time by the timer means after the completion of the calculation processing operations, and then enters the sleep state.

18. A communication control apparatus according to claim 16, wherein the reference time determining means is a down-counter.

6. A communication control apparatus comprising:

a communication circuit for receiving communication signals through an antenna;

a CPU, coupled to the communication circuit, for performing processing when the communication signals are received from the communication circuit and for entering a sleep state when a condition has been satisfied upon the completion of the processing; and

timer means, coupled to the CPU, including a self oscillator comprising a semiconductor element for generating clock pulses without using a crystal oscillator, and measuring a sleep time of the CPU by counting the clock pulses;

the CPU including sleep time calibrating means for correcting a clock count value of the timer means only once by obtaining an error contained in the clock pulses based on reference signals externally inputted at a specified time interval upon the determination that the condition for the CPU for entering the sleep state has been satisfied.

7. A communication control apparatus according to claim 6, wherein the timer means operates only when determining that the condition for the CPU for entering the sleep state has been satisfied.

8. A communication control apparatus according to claim 6, wherein the timer means is supplied with an electric power only when determining that the condition for the CPU for entering the sleep state has been satisfied.

9. A communication control apparatus according to claim 6, wherein:

the communication circuit performs radio communications with a ground station through the antenna and includes a communication start determining circuit for determining upon the receipt of specified electric waves from the ground station through the antenna that the apparatus has entered an area where communications with the ground station are possible and outputting a communication start signal; and

the CPU performs the communicating processing, which is transmitting and receiving data to and from the ground station through the communication circuit upon the output of the communication start signal from the communication start determination circuit, and determines that the condition for entering the sleep state has been satisfied upon the completion of the communication processing.

10. A communication control apparatus according to claim 9, wherein the communication control apparatus is applied to a responder of a toll road charging system.

11. A communication control apparatus according to claim 6, wherein the CPU performs the processing according to a control program using reference clock pulses from an externally connected oscillator and enters the sleep state by cutting off the reference clock pulses to the CPU.

12. A communication apparatus according to claim 11, wherein the reference signals externally inputted at the specified time interval are the reference clock pulses from the externally connected oscillator.