Adaptive 128-bit floating point load and store operations for quadruple precision compatibility

• US 5,729,724 A
• Filed: 12/20/1995
• Issued: 03/17/1998
• Est. Priority Date: 12/20/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mulder, Hans, Alpert, Donald, Sharangpani, Harshvardhan
• Primary Examiner(s): Harrell, Robert B.
• Assistant Examiner(s): Maung, Zarni
• Application Number:
  US08/580,035
• Time in Patent Office: 818 Days
• Field of Search: 395/563, 364/748, 364/752, 364/761, 364/736
• US Class Current: 712/222
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.

Claims

1. In a processing unit utilized for performing floating point numeric calculations, an apparatus for transferring data between a floating point unit and a memory in which said memory is mapped to receive a floating point word of a first precision format comprising:

a floating point register, having a register bit length for supporting a floating point word length of a second precision format, but in which said second precision format is of lower precision format and shorter in bit-length than said first precision format;

a load/store unit coupled to said memory and to said register for providing a store operation in response to a store instruction and a load operation in response to a load instruction for transferring data between said memory and said register;

wherein during a store operation, data bits in said register are stored into a location in said memory at most significant bit positions of a memory boundary based on said first precision format; and

during a load operation, data bits in said location in memory corresponding to said bits from said register are restored to said register.

2. The apparatus of claim 1 wherein said second precision format and said register are of 80 bits and said first precision format and said memory location for storing said floating point word are of 128 bits.

3. The apparatus of claim 2 wherein said data bits from said register occupy bit positions 48 through 127 in said location in memory and bit positions 0 through 47 are filled by said place holder value.

4. The apparatus of claim 3 wherein said place holder value has a value of binary zero.

5. The apparatus of claim 4 wherein said processing unit is based on a x86 microprocessor architecture.

6. A microprocessor having a capability of performing floating point numeric calculations in which data of a lower precision word format is transferred to and from a location in memory having a word boundary for a longer bit-length word corresponding to a higher precision word format comprising:

a floating point register, having a register bit-length for supporting a floating point word of said lower precision word format, but not of said higher precision word format;

a load/store unit coupled to said memory and to said register for providing a store operation in response to a store instruction and a load operation in response to a load instruction for transferring data between said memory and said register;

wherein during a store operation, data bits in said register are stored into said location in said memory at most significant bit positions of a memory boundary based on said higher precision word format and wherein said load/store unit stores a place holder value to remaining bit positions at said location in memory; and

during a load operation, data bits in said location in memory corresponding to said bits from said register are restored to said register and wherein remaining place holder bits are discarded by said load/store unit.

7. The microprocessor of claim 6 wherein said lower precision word format and said register are of 80 bits, representing an extended precision word format, and said higher precision word format and said memory location are of 128 bits, representing a quadruple precision word format.

8. The microprocessor of claim 7 wherein said data bits from said register occupy bit positions 48 through 127 in said location in memory and bit positions 0 through 47 are filled by said place holder value.

9. The microprocessor of claim 8 wherein said place holder value has a value of binary zero.

10. The microprocessor of claim 9 wherein its processor architecture is based on a x86 microprocessor architecture.

11. A microprocessor having a capability of performing floating point numeric calculations in which data of a lower precision word format is transferred to and from a location in memory having a word boundary for a longer bit-length word corresponding to a higher precision word format comprising:

register means, having a register bit-length capable of storing a floating point word of said lower precision word format, but not of said higher precision word format;

load and store means coupled to said memory and to said register means for providing a store operation in response to a store instruction and a load operation in response to a load instruction for transferring data between said memory and said register means;

wherein during a store operation, data bits in said register means are stored into said location in said memory at most significant bit positions of a memory boundary based on said higher precision word format and wherein said load/store means stores a place holder value to remaining bit positions at said location in memory; and

during a load operation, data bits in said location in memory corresponding to said bits from said register means are restored to said register means and wherein remaining place holder bits are discarded by said load/store means.

12. The microprocessor of claim 11 wherein said lower precision word format and said register means are of 80 bits, representing an extended precision word format, and said higher precision word format and said memory location are of 128 bits, representing a quadruple precision word format.

13. The microprocessor of claim 12 wherein said data bits from said register means occupy bit positions 48 through 127 in said location in memory and bit positions 0 through 47 are filled by said place holder value.

14. The microprocessor of claim 13 wherein said place holder value has a value of binary zero.

15. The microprocessor of claim 14 wherein its processing architecture is based on a x86 microprocessor architecture.

16. A computer having a capability of performing floating point numeric calculations utilizing different precision formats, wherein its processor does not have the circuitry to support floating point numeric computations based on a first precision format, but said processor is capable of supporting floating point numeric computations based on a second and lower precision format, an apparatus in said processor for transferring data, having a bit-length corresponding to said second precision format, to and from a location in memory which has an architecture to store floating point values based on said first precision format that is of longer bit-length than said second precision format comprising:

a floating point register, having a register bit-length for supporting a floating point word of said second precision format, but not for said first precision format;

a load/store unit coupled to said memory and to said register for providing a store operation in response to a store instruction and a load operation in response to a load instruction for transferring data between said memory and said register;

wherein during a store operation, data bits in said register are stored into said location in said memory at most significant bit positions of a memory boundary based on said first precision format and wherein said load/store unit stores a place holder value to remaining bit positions at said location in memory; and

during a load operation, data bits in said location in memory corresponding to said bits from said register are restored to said register and wherein remaining place holder bits are discarded by said load/store unit;

such that data transfer of said second precision format is achieved by instructions for operating on said first precision format.

17. The computer of claim 16 wherein said second precision format and said register are of 80 bits and said first precision format and said memory location are of 128 bits.

18. The computer of claim 17 wherein said data bits from said register occupy bit positions 48 through 127 in said location in said memory and bit positions 0 through 47 are filled by said place holder value.

19. The computer of claim 18 wherein said place holder value has a value of binary zero.

20. The computer of claim 19 wherein said processor is based on a x86 microprocessor architecture.