Associative network method and apparatus

• US 5,729,754 A
• Filed: 05/17/1995
• Issued: 03/17/1998
• Est. Priority Date: 03/28/1994
• Status: Expired due to Fees

• Current Assignee: Mark D. Estes
• Original Assignee: Mark D. Estes
• Inventors: Estes, Mark D.
• Primary Examiner(s): SHAH, ALPESH
• Application Number:
  US08/443,282
• Time in Patent Office: 1,035 Days
• Field of Search: 395/21, 395/200.02, 395/200.1, 395/200.15, 395/200.2, 395/800, 370/14, 370/53, 370/54, 370/67, 370/85.7, 370/95.1, 340/825.06, 340/826
• US Class Current: 712/15
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/8038 Associative processors

Abstract

A reconfigurable, associative network apparatus and method. During a configuration phase of the associative network apparatus, active signals corresponding to wanted input patterns are configured as an associative network and distinguished from signals corresponding to unwanted input patterns; wanted input patterns can be further associated with output patterns corresponding to wanted responses. During an operational phase of a previously configured associative network, input patterns are formed from signals produced by one or a plurality of activated inputs. Selected input patterns are then filtered from a set of possible input patterns, and output patterns are obtained in response to a particular set of connections between input and output signals. An adaptive chord keyboard system, representative of a large class of polymorphic control systems, is disclosed as an illustrative embodiment permitting dynamic association of key codes to symbol sets for readily adapting to user capabilities, limitations, and preferences.

Claims

1. An associative network apparatus for enabling a plurality of elements arranged in a fixed physical configuration to be dynamically reconfigured, responsive to user preferences, into a plurality of logical configurations for recall based on user-selected associations, comprising:

a plurality of input circuits for providing a plurality of input signals, with each of the plurality of input signals having a value corresponding to one of a logical one and a logical zero;

a plurality of electrically-activated elements including,

a first set of elements, electrically coupled to each of said plurality of input circuits, having an input signal corresponding to a logical one; and

a second set of elements, electrically coupled to each of said plurality of input circuits, having an input signal corresponding to a logical zero;

a data bus, electrically coupled to each of said plurality of input circuits, for conveying the plurality of input signals to said plurality of electrically-activated elements;

a control bus, electrically coupled to each of said plurality of input circuits, for controlling the plurality of input signals;

an input control circuit, electrically coupled to each of said plurality of input circuits and to said control bus, for controlling the plurality of input circuits; and

means for switching a logical polarity of the plurality of input circuits to select, responsive to said input control circuit, a set of elements, the set of elements selected being one of the first set of elements and the second set of elements.

2. The associative network apparatus as set forth in claim 1, said means for switching comprising:

a plurality of logical polarity input switches, each of said plurality of logical polarity input switches electrically coupled to a respective input circuit as a configuration control mechanism, the configuration control mechanism electrically coupled to said plurality of electrically-activated elements for setting and resetting a logical polarity of the respective input circuit, the configuration control mechanism also electrically coupled to said data bus; and

a polarity control circuit, electrically coupled to each of said plurality of logical polarity input switches and to said control bus.

3. The associative network apparatus as set forth in claim 2, with said data bus providing a first polarity selection signal for reversing a logical polarity of a respective input circuit, and with said data bus providing a second polarity selection signal for restoring the logical polarity of the respective input circuit.

4. The associative network apparatus of claim 3, with said control bus providing a control signal corresponding to a polarity switch enable signal.

5. The associative network apparatus as set forth in claim 2, further comprising:

a plurality of selection level input circuits, each of said plurality of selection level input circuits electrically coupled to each of said plurality of electrically-activated elements and to said data bus for setting and resetting an activation selection level;

a selection level control circuit, electrically coupled to the control bus and to each of said plurality of selection level input circuits, for controlling said plurality of selection level input circuits; and

a multiplicity of electrically-activated elements within said plurality of electrically-activated elements selected responsive to a set of input signals comprising a partial logical name corresponding to the selected multiplicity of electrically-activated elements.

6. The associative network apparatus as set forth in claim 2, further comprising:

a network element set/reset input circuit, electrically coupled to each of said plurality of electrically-activated elements and to said data bus for setting and resetting a state of a selected element; and

a network element set/reset control circuit, electrically coupled to the control bus and to said network element set/reset input circuit, for controlling said network element set/reset input circuit.

7. The associative network apparatus as set forth in claim 6 with said network element set/reset input circuit, responsive to said network element set-reset control circuit, for globally resetting a state of each of said plurality of electrically-activated elements to a known state.

8. The associative network apparatus as set forth in claim 2, further comprising:

a plurality of output pattern circuits electrically coupled to said data bus, each of said plurality of output pattern circuits electrically coupled to each of said plurality of electrically-activated elements;

an output pattern control circuit, electrically coupled to said control bus and to said plurality of output pattern circuits; and

a plurality of logical polarity output switches, electrically coupled to said plurality of logical polarity input switches, respectively, for controlling logical polarity states for output patterns in correspondence with logical polarity states of input patterns.

9. The associative network apparatus as set forth in claim 8, further comprising:

a plurality of output configuration circuits electrically coupled to said data bus and to said plurality of output pattern circuits;

a plurality of gated buffer control circuits electrically coupled between said plurality of output configuration circuits and said plurality of output pattern circuits, respectively;

an output configuration control circuit electrically coupled to said control bus and to said plurality of output configuration circuits;

each of said plurality of input circuits configurable as at least one of an input and an output for relating a plurality of input patterns to a corresponding plurality of output patterns, respectively.

10. An interactive network apparatus, arranged in a fixed physical configuration, dynamically reconfigurable to a plurality of logical configurations for user-selected associative recall, comprising:

a plurality of electrically-activated elements;

a plurality of input circuits, electrically coupled to said plurality of electrically-activated elements;

a data bus, electrically coupled to each of said plurality of input circuits, for transmitting a plurality of input signals, with a particular set of input signals comprising a logical name corresponding to and activating a particular electrically-activated element of said plurality of electrically-activated elements;

a control bus, electrically coupled to each of said plurality of input circuits, for enabling the plurality of input signals;

a plurality of logical polarity input switches, each of said plurality of logical polarity input switches electrically coupled to a respective input circuit as a configuration control mechanism, the configuration control mechanism electrically coupled to said plurality of electrically-activated elements for setting and resetting a logical polarity of the respective input circuit to determine a network configuration based on a logical polarity of input patterns, the configuration control mechanism also electrically coupled to said data bus and to said control bus;

a polarity control circuit, electrically coupled to each of said plurality of logical polarity input switches and to said control bus;

an input control circuit, electrically coupled to each of said plurality of input circuits and to said control bus;

a plurality of selection level input circuits, electrically coupled to said plurality of electrically-activated elements, respectively, and to said data bus, each of said plurality of selection level input circuits responsive to an activation selection level;

a selection level control circuit, electrically coupled to said control bus and to each of said plurality of selection level input circuits, for setting and resetting the activation selection level, the activation selection level allowing a multiplicity of electrically-activated elements to be selected concurrently responsive to a partial logical name corresponding to the multiplicity of electrically-activated elements;

a network element set/reset input circuit, electrically coupled to said plurality of electrically-activated elements and to said data bus, for setting and resetting a state of an electrically-activated element; and

a network element set/reset control circuit, electrically coupled to said control bus and to said network element set/reset input circuit for clearing a state set by at least one of said input control circuit, said logical polarity control circuit, said selection level control circuit, and said network element set/reset input circuit and for resetting the state to a known state.

11. The interactive network apparatus as set forth in claim 10, further comprising:

a plurality of output pattern circuits, electrically coupled between said data bus and said plurality of electrically-activated elements;

an output pattern control circuit, electrically coupled to said control bus and to said plurality of output pattern circuits;

a plurality of logical polarity switches electrically coupled to said plurality of logical polarity input switches, respectively, for controlling logical polarity states of output patterns responsive to the network configuration determined by the logical polarity, of input patterns;

a plurality of output configuration circuits, electrically coupled to said data bus and to said plurality of output pattern circuits;

a plurality of gated buffer control circuits, electrically coupled between said plurality of output configuration circuits and said plurality of output pattern circuits; and

an output configuration control circuit, electrically coupled to said control bus and to said plurality of output configuration circuits, for configuring each of said plurality of output circuits as one of a network input and a network output for relating a plurality of input patterns to a corresponding plurality of output patterns.

12. The interactive network apparatus as set forth in claims 9 or 11, further comprising:

a plurality of actuator means with each of said plurality of actuator means coupled to said data bus for forming logically-related input activations;

first memory means coupled to each of said plurality of actuator means for storing a first state corresponding to a quiescent state for a particular actuator and for storing a second state corresponding to an activation event for a particular actuator;

second memory means coupled to each of said plurality of actuator means for storing a first state corresponding to one of a quiescent state and an activation event for a particular actuator and for storing a second state corresponding to a deactivation event for a particular actuator; and

adaptively reconfigurable means for controlling asynchronously formed messages responsive to a plurality of logically-related input activations permitting any number of actuator means, including all actuator means, to be activated and deactivated simultaneously or sequentially in any sequence.

13. The interactive network apparatus as set forth in claim 12, further comprising light emitting means and with said plurality of actuator means including:

light sensitive means, mounted to said plurality of actuator means and responsive to said light emitting means; and

logic means, electrically coupled to said light sensitive means, for logically coupling said light sensitive means to said first and second memory means;

said light emitting means momentarily activating, responsive to an activation event, said light sensitive means and said light emitting means deactivating, responsive to a deactivation event, said light sensitive means, sensing a single activation/deactivation event as two separate states.

14. A process for dynamically configuring a polymorphic network apparatus and for selecting an element of a plurality of elements configured as an N-dimensional object space, said polymorphic network apparatus including a plurality of input circuits, a data bus with a plurality of signal paths, and a control bus, comprising the steps of:

configuring the plurality of elements for a logical N-dimensional configuration;

inputting, using the data bus, a polarity selection signal for each of the plurality of input circuits;

setting, responsive to a first setting of the polarity selection signals, a logical polarity for each of the plurality of input circuits, respectively;

activating, responsive to the first setting of the logical polarity defining a first partial logical name, a first selected set of elements within the plurality of elements, the first selected set of elements defined by the first partial logical name;

switching responsive to a second setting of the polarity selection signals, a logical polarity for a plurality of input circuits, respectively; and

activating, responsive to the second setting of logical polarity defining a second partial logical name, a second selected set of elements within the plurality of elements, the second selected set of elements defined by the second partial logical name.

15. A process for dynamically configuring a polymorphic network apparatus having a plurality of elements, arranged in a fixed physical configuration, into a plurality of logical configurations for associative recall, said polymorphic network apparatus including a plurality of input circuits, a data bus with a plurality of signal paths, and a control bus, comprising the steps of:

configuring a plurality of elements arranged in a fixed, physical, network configuration for a logical N-dimensional configuration;

inputting one of a first polarity selection signal and a second polarity selection signal for each of the plurality of signal paths, with the first polarity selection signal corresponding to reversing a logical polarity of a related input circuit and the second polarity selection signal corresponding to restoring the logical polarity of the related input circuit;

inputting a control signal on the control bus corresponding to a polarity switch enable signal, with the plurality of signal paths accessed by a plurality of polarity control switches;

inputting an output pattern configuration signal, corresponding to an input data pattern, on the data bus;

inputting a control signal, corresponding to an input/output pattern configuration enable signal, on the control bus with the plurality of signal paths accessed by a plurality of output pattern configuration circuits; and

associating, during a configuration phase of an associative process, active signals corresponding to wanted input patterns and distinguishing the active signals corresponding to wanted input patterns from signals corresponding to unwanted input patterns.

16. The process as set forth in claim 15 further comprising the steps of:

inputting a reference pattern signal, corresponding to an input pattern and an associated output pattern, on the data bus;

inputting a control signal, corresponding to an input pattern enable signal, on the control bus with the plurality of signal paths accessed by a plurality of input circuits; and

associating, during a configuration phase of an associative process, wanted input patterns with output patterns corresponding to wanted responses.

17. The process as set forth in claim 16 further comprising the steps of:

inputting an input pattern signal, corresponding to an input data pattern, on the data bus;

inputting a control signal, corresponding to an input data pattern enable signal, on the control bus with the plurality of signal paths accessed by a plurality of input pattern configuration circuits;

forming, during an operational phase of a previously configured associative network, input patterns from signals produced by a plurality of activated inputs;

filtering selected input patterns from a set of possible input patterns; and

determining output patterns in response to a particular set of connections between input and output signals.

18. The process as set forth in claim 17 further comprising the steps of:

inputting a control signal, corresponding to an output pattern enable signal, on the control bus with the plurality of signal paths accessed by a plurality of output pattern circuits; and

obtaining output patterns in response to a particular set of connections between input and output signals.

19. A process for dynamically configuring and operating a dynamically reconfigurable polymorphic network for mapping a first set of codewords to a second set of codewords, said polymorphic network apparatus including a plurality of input circuits, a data bus having a plurality of signal paths, and a control bus, comprising the steps of:

configuring a plurality of elements arranged in a fixed, physical network configuration for a logical N-dimensional configuration;

inputting one of a first polarity selection signal and a second polarity selection signal for each of the plurality of signal paths with the first polarity selection signal corresponding to reversing a logical polarity of a related input circuit and the second polarity selection signal corresponding to restoring the logical polarity of the related input circuit;

inputting a control signal, corresponding to a polarity switch enable signal, on the control bus with the plurality of signal paths accessed by a plurality of polarity control switches;

inputting an output pattern configuration signal, corresponding to an input data pattern, on the data bus;

inputting a control signal, corresponding to an input/output pattern configuration enable signal, on the control bus with the plurality of signal paths accessed by a plurality of output pattern configuration circuits;

inputting a reference pattern signal, corresponding to an input pattern and an associated output pattern, on the data bus;

inputting a control signal, corresponding to an input pattern enable signal, on the control bus with the plurality of signal paths accessed by the plurality of input circuits; and

generating, responsive to a particular input pattern of said first set of codewords, an output pattern of said second set of codewords.

20. A process for adaptively configuring a keyboard for particular user capabilities and preferences using an associative network apparatus including a data bus having a plurality of signal paths, a control bus, and a plurality of electrically-activated elements arranged in a fixed, physical network configuration, with user capabilities and preferences determining a range of available key layout configurations, the process comprising the steps of:

a. configuring the plurality of electrically-activated elements for a mixed resolution, N-dimensional logical configuration;

b. inputting on the data bus an output pattern configuration signal, corresponding to an input data pattern, representing a plurality of operational states;

c. inputting on the control bus a control signal, corresponding to an input/output pattern configuration enable signal, with the plurality of signal paths accessed by a plurality of output pattern configuration circuits;

d. inputting on the data bus a first reference pattern signal, corresponding to an input pattern representing a first set of user preferences and capabilities and an associated output pattern representing one of a plurality of operational states;

e. inputting on the control bus a control signal, corresponding to an input pattern enable signal, with the plurality of signal paths accessed by a plurality of input circuits;

f. inputting on the data bus a next reference pattern signal, corresponding to an input pattern representing a next set of user preferences and capabilities and an associated output pattern representing one of a plurality of operational states;

g. inputting on the control bus a control signal, corresponding to an input pattern enable signal, with the plurality of signal paths accessed by a plurality of input circuits; and

h. repeating steps f and g for configuring an association between all desired reference patterns for user preferences and capabilities and associated respective output patterns.

21. The process as set forth in claim 20, with a particular user'"'"'s capabilities and preferences for operating a keyboard determining a range of available key input patterns for a particular key layout configuration, for adaptively configuring a keyboard for user capabilities and preferences relating to the digits of one hand, the process further comprising the steps of:

inputting on the data bus an input pattern signal corresponding to an input data pattern representing a particular user'"'"'s ability to press and release a combination of keys for an input key pattern; and

inputting on the control bus a control signal corresponding to an input data pattern enable signal, with the plurality of signal paths accessed by a plurality of input pattern configuration circuits.

22. A process for adaptively configuring a keyboard for user capabilities and preferences relating to the digits of one hand, using a reconfigurable associative network apparatus including a data bus having a plurality of signal paths, a control bus, and a plurality of elements arranged in a fixed, physical network configuration, comprising the steps of:

a. configuring the plurality of elements for a logical N-dimensional configuration with each dimension corresponding to a two-state key activation associated with a particular digit of one hand;

b. inputting, on the data bus, an output pattern configuration signal corresponding to an input data pattern representing a response to a plurality of possible key activations for an input key pattern;

c. inputting, on the control bus, a control signal corresponding to an input/output pattern configuration enable signal, with the plurality of signal paths accessed by a plurality of output pattern configuration circuits;

d. inputting, on the data bus, a first reference pattern signal corresponding to an input pattern representing a first combination of keys for an input key pattern;

e. inputting, on the control bus, a control signal corresponding to an input pattern enable signal, with the plurality of signal paths accessed by a plurality of input circuits;

f. inputting, on the data bus, a next reference pattern signal corresponding to an input pattern representing a next combination of keys for an input key pattern;

g. inputting, on the control bus, a control signal corresponding to an input pattern enable signal, with the plurality of signal paths accessed by a plurality of input circuits; and

h. repeating steps f and g for configuring an association between a plurality of combinations of keys for input key patterns and a respective plurality of output patterns.

23. The process as set forth in claim 22 for adaptively configuring a keyboard for particular key patterns representing input and output pattern associations corresponding to input patterns formed by key activations of a first hand, further comprising the step of:

repeating steps a through h for adaptively configuring key patterns representing input and output pattern associations corresponding to input patterns formed by key activations of a second hand;

forming, for particular key patterns of a first hand, input patterns associated with output patterns corresponding to a first component of a structured symbol name and, for particular key patterns of a second hand, forming input patterns associated with output patterns corresponding to a second component of a structured symbol name, and with said first and second components of a structured symbol name further corresponding to particular symbol set instances of a symbol system.

24. The process as set forth in claim 23, further comprising the steps of:

inputting on the data bus a first input pattern signal corresponding to an input data pattern representing key patterns formed by key activations of a first hand; and

inputting on the data bus a second input pattern signal corresponding to an input data pattern representing key patterns formed by key activations of a second hand;

inputting on the control bus a control signal corresponding to an input data pattern enable signal, with the plurality of signal paths accessed by a plurality of input pattern configuration circuits; and

determining output patterns corresponding to first and second components of a structured symbol name for particular symbol set instances of a symbol system.

25. A process for adaptively configuring a plurality of logically-related input activations permitting any number of actuator means, including all actuator means, to be activated and deactivated simultaneously or sequentially in any sequence, for configuring an associative network apparatus for controlling asynchronously formed message transitions in response to a plurality of logically-related input activations, comprising the steps of:

a. configuring a plurality of elements arranged in a fixed, physical network configuration for a logical N-dimensional configuration with each dimension corresponding to a two-state key activation;

b. inputting an output pattern configuration signal on a data bus corresponding to an input data pattern representing a response to a plurality of possible key activations for an input key pattern;

c. inputting a control signal on a control bus corresponding to an input/output pattern configuration enable signal, with a plurality of signal paths within the data bus accessed by a plurality of output pattern configuration circuits;

d. inputting a first reference pattern signal on the data bus corresponding to an input pattern corresponding to a first combination of keys for an input key pattern;

e. inputting a control signal on the control bus corresponding to an input pattern enable signal, with the plurality of signal paths accessed by a plurality of input circuits;

f. inputting a next reference pattern signal on the data bus corresponding to an input pattern corresponding to a next combination of keys for an input key pattern;

g. inputting a control signal on the control bus corresponding to an input pattern enable signal, with the plurality of signal paths accessed by a plurality of input circuits; and

h. repeating steps f and g for configuring an association between a plurality of reference patterns for possible combinations of keys for input key patterns and respective output patterns.

26. A process for adaptively configuring a keyboard for a particular symbol system, comprising the steps of:

a. configuring a plurality of elements arranged in a fixed, physical network configuration for a mixed-resolution, N-dimensional logical configuration with each dimension corresponding to at least one key pattern;

b. inputting an output pattern configuration signal on a data bus corresponding to an input data pattern representing a response to a plurality of possible key activations for an input key pattern;

c. inputting a control signal on a control bus corresponding to an input/output pattern configuration enable signal, with signal paths of the data bus accessed by a plurality of output pattern configuration circuits;

d. inputting a first reference pattern signal on the data bus corresponding to an input pattern representing a first combination of keys for an input key pattern associated with an instance of a plurality of symbols in a symbol system;

e. inputting a control signal on said control bus corresponding to an input pattern enable signal, with the signal paths of the data bus accessed by a plurality of input circuits;

f. inputting a next reference pattern signal on the data bus corresponding to an input pattern representing a next combination of keys for an input key pattern associated with an instance of a plurality of symbols in a symbol system;

g. inputting a control signal on the control bus corresponding to an input pattern enable signal, with the signal paths of the data bus accessed by a plurality of input circuits; and

h. repeating steps f and g for configuring an association between selected reference patterns for possible combinations of keys for input key patterns and respective symbols.