System and method for accessing peripheral devices on a non-functional controller

• US 5,729,767 A
• Filed: 10/07/1994
• Issued: 03/17/1998
• Est. Priority Date: 10/07/1994
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Lory, Jay, Jones, Craig S., Pecone, Victor K.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/319,689
• Time in Patent Office: 1,257 Days
• Field of Search: 395/325, 395/275, 395/280, 395/882, 371/10, 371/22.3, 364/132
• US Class Current: 710/62
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence

Abstract

A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot, the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

Claims

1. A method for accessing a memory in a bus adapter of a computer system, the computer system comprising a CPU, a first bus coupled to the CPU, and the bus adapter coupled to the first bus, wherein the bus adapter comprises a bus interface for coupling to said first bus, a second bus coupled to said bus interface, a local processor coupled to said second bus, a peripheral bus coupled to said bus interface, and the memory coupled to said peripheral bus, the method comprising:

configuring said memory coupled to said peripheral bus to map to said bus interface, wherein said memory is accessible by said CPU when said memory is mapped to said bus interface;

said CPU beginning a startup routine after said configuring said memory, wherein said CPU detects said memory coupled to said peripheral bus as being mapped to said bus interface;

said CPU accessing said memory coupled to said peripheral bus in said bus adapter after said CPU beginning said startup routine;

reconfiguring said memory to unmap said memory from said bus interface after said CPU accessing said memory, wherein said memory is accessible to said local processor comprised in said bus adapter in response to said reconfiguring; and

said CPU restarting after said reconfiguring said memory.

2. The method of claim 1, wherein said bus interface comprises a first bus interface for coupling to said first bus, a second bus interface coupled to said first bus interface and said second bus, and a peripheral bus interface coupled to said first bus interface and said second bus interface, wherein said peripheral bus is coupled to said peripheral bus interface;

wherein said CPU accessing comprises said CPU accessing said first bus interface, wherein said first bus interface accesses said memory in response to said CPU accessing said first bus interface.

3. The method of claim 1, wherein said local processor is inoperable during said CPU accessing said memory coupled to said peripheral bus.

4. The method of claim 1, wherein said second bus is inaccessible during said CPU accessing said memory coupled to said peripheral bus.

5. The method of claim 1, wherein said CPU accessing comprises accessing said memory without accessing said second bus.

6. The method of claim 1, wherein said bus adapter is inoperable during said CPU accessing.

7. The method of claim 1, wherein said memory is Flash memory storing boot and initialization code for said bus adapter;

wherein said CPU accessing comprises writing new data to said Flash memory.

8. The method of claim 1, wherein said memory is non-volatile random access memory;

and

wherein said CPU accessing comprises reading failure data from said nonvolatile random access memory.

9. The method of claim 1, wherein said configuring said memory comprises setting a jumper.

10. The method of claim 1, wherein said first and said second buses comply with a peripheral component interconnect (PCI) bus standard.

11. The method of claim 1, wherein said bus adapter is a small computer systems interface adapter.

12. A method for installing and programming a memory in a controller of a computer system, the computer system comprising a CPU, a first bus coupled to the CPU, and the controller coupled to the first bus, wherein the controller comprises a bus interface for coupling to said first bus, a second bus coupled to said bus interface, a jumper coupled to said bus interface, a local processor coupled to said second bus, a peripheral bus, the method comprising:

installing said memory in said controller of said computer system, wherein said memory is not programmed;

configuring said memory after said installing said memory to map said memory to said bus interface, wherein said memory is accessible by said CPU when said memory is mapped to said bus interface;

said CPU beginning a startup routine after said configuring said memory;

said CPU accessing said bus interface to write data to said memory in said controller after said CPU beginning said startup routine;

reconfiguring said memory after said CPU accessing said bus interface to unmap said memory from said bus interface, wherein said memory is accessible to said local processor; and

said CPU restarting after reconfiguring said memory.

13. The method of claim 12, wherein said bus interface comprises a first bus interface for coupling to said first bus, a second bus interface coupled to said first bus interface and said second bus, and a peripheral bus interface coupled to said first bus interface and said second bus interface;

wherein said peripheral bus is coupled to said peripheral bus interface;

wherein said CPU accessing comprises said CPU accessing said first bus interface, wherein said first bus interface writes to said memory in response to said CPU accessing said first bus interface.

14. The method of claim 12, wherein said local processor is inoperable during said CPU accessing.

15. The method of claim 12, wherein said controller is inoperable during said CPU accessing.

16. The method of claim 12, wherein said memory is Flash memory storing boot and initialization code for said controller;

wherein said CPU accessing comprises writing data to said Flash memory.