Semiconductor device MOS gated

• US 5,731,604 A
• Filed: 10/08/1996
• Issued: 03/24/1998
• Est. Priority Date: 09/01/1994
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/727,142
• Time in Patent Office: 532 Days
• Field of Search: 257/341, 257/342, 257/343, 257/336, 257/138, 257/153, 257/382, 257/383, 257/329, 257/330
• US Class Current: 257/153
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask to sequentially form a cell body and a source region within the cell body, and a second mask step to form, by a silicon etch, a central opening in the silicon surface at each cell and to subsequently undercut the oxide surrounding the central opening. A contact layer then fills the openings of each cell to connect together the body and source regions. Only one critical mask alignment step is used in the process.

Claims

1. A MOS gated semiconductor device;

said device comprising a wafer of monocrystalline silicon having at least one flat surface of a first conductivity type;

a plurality of spaced cells symmetrically distributed over and formed into said one flat surface;

each of said cells having a substantially identical structure, including a first region of a second conductivity type, which is of opposite conductivity type to said first conductivity type, having a first depth and a first lateral extent and extending from said first surface and into the body of said wafer;

a second region of said first conductivity type formed at least partly within said first region and extending from said first surface;

a third region of said second conductivity type that extends from said first surface and which is deeper and wider than and has a lower concentration than that of said first region;

the boundary of said second region being laterally spaced from the boundary of said third region at least along said first surface;

a gate insulation layer overlying at least the area on said first surface formed between the laterally spaced second and third regions, a gate electrode overlying said gate insulation layer;

a central depression etched into each cell which extends from said first surface, through said second region and into said first region; and

a single contact layer extending over said first surface and into each of said central depressions, thereby to electrically connect together said first and second regions.

2. The device of claim 1, wherein said first conductivity type is N-type, and said second conductivity type is P-type.

3. The device of claim 1 wherein said first and second regions are heavily doped with said impurities of said second and first conductivity types, respectively.

4. The device of claim 1 wherein said plurality of spaced cells have identical shapes.

5. The device of claim 1 further comprising an overlying insulation layer arranged between said gate electrode and said contact layer.

6. The device of claim 1 wherein said contact layer is a main electrode layer for said MOS gated semiconductor device.

7. An MOS gated semiconductor device comprising:

a layer of gate insulation material formed atop a silicon substrate;

a layer of polysilicon deposited atop said layer of gate insulation material, said layer of gate insulation material and said layer of polysilicon having a plurality of corresponding spaced openings;

first diffused regions formed of impurities of a first conductivity type introduced into, and extending from, surface regions of said silicon substrate located beneath said corresponding spaced openings in said layers of gate insulation material and polysilicon and into the body of said substrate;

second diffused regions formed of impurities of a second conductivity type, which is of opposite conductivity type to said first conductivity type, introduced into, and extending from, said corresponding surface regions of said silicon substrate;

said first diffused regions having a final depth that is less than that of said second diffused regions;

third diffused regions formed of impurities of said second conductivity type introduced into, and extending from, said surface regions of said silicon substrate;

said third diffused regions being deeper and wider than and having a lower concentration than that of said second diffused regions;

an overlaying insulation layer having openings formed therein which expose respective underlying areas of said surface regions of said silicon substrate;

said underlying areas of said surface regions of said silicon substrate having depressions formed therein of a depth greater than the depth of said first diffused regions;

said second openings exposing further portions of the surface of said silicon substrate which are adjacent to and which surround said depressions in said underlying areas of said surface regions of said silicon substrate; and

a single conductive layer deposited over said overlaying insulation layer and in said openings in said overlaying insulation layer and which contacts said second diffused regions at the bottom of said depressions and said first diffused regions at the upper portions of said depressions and at said further portions of the surface of said silicon substrate.

8. The device of claim 7 wherein said first conductivity type is N-type, and said second conductivity type is P-type.

9. The device of claim 7 wherein said first and second diffused regions are heavily doped with said impurities of said first and second conductivity types, respectively.

10. The device of claim 7 wherein said layer of gate insulation material is silicon dioxide.

11. The device of claim 7 wherein said plurality of spaced openings in said polysilicon layer have identical shapes.

12. The device of claim 11 wherein said openings are selected from the group consisting of closed polygons and elongated strips.

13. The device of claim 7 wherein said overlying insulation layer is a low temperature oxide.

14. The device of claim 7 wherein said conductive layer is a main electrode layer.

15. The device of claim 7 wherein said openings in said overlying insulation layer have curved side walls such that the diameter at the top of a respective one of said openings is greater than the diameter at the bottom of said respective opening.

16. The device of claim 15 wherein said depressions in said silicon substrate have curved side walls such that the diameter at the top of a respective one of said depressions is greater than the diameter at the bottom of said respective depression.

17. An MOS gated semiconductor device comprising:

a layer of gate insulation material formed atop a silicon substrate;

a layer of polysilicon deposited atop said layer of gate insulation material, said layer of gate insulation material and said layer of polysilicon having a plurality of corresponding spaced openings;

first diffused regions formed of impurities of a first conductivity type introduced into, and extending from, surface regions of said silicon substrate located beneath said corresponding spaced openings in said layers of gate insulation material and polysilicon and into the body of said substrate;

an overlaying insulation layer having openings formed therein which expose respective underlying areas of said surface regions of said silicon substrate;

said underlying areas of said surface regions of said silicon substrate having depressions formed therein of a depth greater than the depth of said first diffused regions;

said second openings exposing further portions of the surface of said silicon substrate which are adjacent to and which surround said depressions in said underlying areas of said surface regions of said silicon substrate;

second diffused regions formed of impurities of a second conductivity type, which is of opposite conductivity type to said first conductivity type, introduced into, and extending from, said depressions and into said further portions of the surface of said silicon substrate;

said first diffused regions having a final depth that is less than that of said second diffused regions; and

a single conductive layer deposited over said overlaying insulation layer and in said openings in said overlaying insulation layer and which contacts said second diffused regions at the bottom of said depressions and said first diffused regions at the upper portions of said depressions and at said further portions of the surface of said silicon substrate.

18. The device of claim 17 further comprising third diffused regions formed of impurities of said second conductivity type introduced into said surface regions of said silicon substrate;

said third diffused regions being deeper and wider than and having a lower concentration than that of said second diffused regions.

19. The device of claim 17, wherein said first conductivity type is N-type, and said second conductivity type is P-type.

20. The device of claim 17 wherein said first and second diffused regions are heavily doped with said impurities of said first and second conductivity types, respectively.

21. The device of claim 17 wherein said layer of gate insulation material is silicon dioxide.

22. The device of claim 17 wherein said plurality of spaced openings in said polysilicon layer have identical shapes.

23. The device of claim 22 wherein said openings are selected from the group consisting of closed polygons and elongated strips.

24. The device of claim 17 wherein said overlying insulation layer is a low temperature oxide.

25. The device of claim 17 wherein said conductive layer is a main electrode layer.