Semiconductor integrated circuit device
First Claim
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1. A semiconductor integrated circuit device comprising:
- a first and a second FETs connected in series with respect to the signal path;
a third FET connected between the node of said first and second FETs and a ground region;
a first high-impedance element connected between the gate terminal of said first FET and a first control terminal for controlling said first FET and said second FET; and
a second high-impedance element connected between the gate terminal of said second FET and said first control terminal.
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Abstract
In a semiconductor integrated circuit device, particularly in a switch circuit, a first and a second FETs are connected in series with respect to the signal path, and a third FET is connected between the node of these first and second FETs and the ground region. Thereby, low insertion loss, high isolation, and miniaturization of the entire circuit can be realized simultaneously.
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Citations
14 Claims
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1. A semiconductor integrated circuit device comprising:
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a first and a second FETs connected in series with respect to the signal path; a third FET connected between the node of said first and second FETs and a ground region; a first high-impedance element connected between the gate terminal of said first FET and a first control terminal for controlling said first FET and said second FET; and a second high-impedance element connected between the gate terminal of said second FET and said first control terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor integrated circuit device comprising:
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a first and a second FETs connected in series with respect to a first signal path for relating a first signal terminal and a second signal terminal; a third FET connected between the node of said first and second FETs and a first ground region; a first high-impedance element connected between the gate terminal of said first FET and a first control terminal for controlling said first FET and said second FET; a second high-impedance element connected between the gate terminal of said second FET and said first control terminal; a fourth and a fifth FETs connected in series with respect to a second signal path for relating said first signal terminal and a third signal terminal; a sixth FET connected between the node of said fourth and fifth FETs and a second ground region; a third high-impedance element connected between the gate terminal of said fourth FET and a second control terminal for controlling said fourth FET and said fifth FET; and a fourth high-impedance element connected between the gate terminal of said fifth FET and said second control terminal. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification