Semiconductor integrated circuit device

• US 5,731,607 A
• Filed: 04/17/1996
• Issued: 03/24/1998
• Est. Priority Date: 04/24/1995
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kohama, Kazumasa
• Primary Examiner(s): MONIN, DONALD L JR
• Application Number:
  US08/633,431
• Time in Patent Office: 706 Days
• Field of Search: 327/379, 327/384, 327/387, 257/275, 257/364
• US Class Current: 257/275
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

In a semiconductor integrated circuit device, particularly in a switch circuit, a first and a second FETs are connected in series with respect to the signal path, and a third FET is connected between the node of these first and second FETs and the ground region. Thereby, low insertion loss, high isolation, and miniaturization of the entire circuit can be realized simultaneously.

Claims

1. A semiconductor integrated circuit device comprising:

a first and a second FETs connected in series with respect to the signal path;

a third FET connected between the node of said first and second FETs and a ground region;

a first high-impedance element connected between the gate terminal of said first FET and a first control terminal for controlling said first FET and said second FET; and

a second high-impedance element connected between the gate terminal of said second FET and said first control terminal.

2. The semiconductor integrated circuit device according to claim 1, wherein

a part or the entire of a portion, paralleled to an RF signal line at a short distance, out of a biasing DC signal line which has been provided on a semiconductor substrate, is masked with a metal pattern of the ground electric potential which has been provided in such a way that a insulating layer is inserted between them.

3. The semiconductor integrated circuit device according to claim 1, wherein

the ground region connected to said third FET is provided in such a way as to be disconnected from the other ground regions laid on the semiconductor substrate.

4. The semiconductor integrated circuit device according to claim 1, wherein

the source terminals and/or the drain terminals of said first and second FETs are biased from said ground via resistors.

5. The semiconductor integrated circuit device according to claim 1, wherein

said third FET is connected to said ground region via capacitance.

6. The semiconductor integrated circuit device according to claim 5, wherein

the source terminals and/or the drain terminals of said first, second, and third FETs are biased via resistors in which one end is connected to the bias line.

7. The semiconductor integrated circuit device according to claim 6, wherein

capacitance is connected between said bias line and said ground region, and the impedance of the capacitance is nearly 30% of the impedance of said resistor or less.

8. A semiconductor integrated circuit device comprising:

a first and a second FETs connected in series with respect to a first signal path for relating a first signal terminal and a second signal terminal;

a third FET connected between the node of said first and second FETs and a first ground region;

a first high-impedance element connected between the gate terminal of said first FET and a first control terminal for controlling said first FET and said second FET;

a second high-impedance element connected between the gate terminal of said second FET and said first control terminal;

a fourth and a fifth FETs connected in series with respect to a second signal path for relating said first signal terminal and a third signal terminal;

a sixth FET connected between the node of said fourth and fifth FETs and a second ground region;

a third high-impedance element connected between the gate terminal of said fourth FET and a second control terminal for controlling said fourth FET and said fifth FET; and

a fourth high-impedance element connected between the gate terminal of said fifth FET and said second control terminal.

9. The semiconductor integrated circuit device according to claim 8, wherein

a part or the entire of a portion, paralleled to an RF signal line at a short distance, out of a biasing DC signal line which has been provided on a semiconductor substrate, is masked with a metal pattern of the ground electric potential which has been provided in such a way that a insulating layer is inserted between them.

10. The semiconductor integrated circuit device according to claim 8, wherein

said first ground region is provided in such a way as to be disconnected from said second ground regions, and also each said first and second ground region is provided in such a way as to be disconnected from the other ground regions laid on the semiconductor substrate.

11. The semiconductor integrated circuit device according to claim 8, wherein:

the source terminals and/or the drain terminals of said first and second FETs are biased from said first ground region via resistors; and

the source terminals and/or the drain terminals of said fourth and fifth FETs are biased from said second ground region via resistors.

12. The semiconductor integrated circuit device according to claim 8, wherein:

said third FET is connected to said first ground region via a first capacitance; and

said sixth FET is connected to said second ground region via a second capacitance.

13. The semiconductor integrated circuit device according to claim 12, wherein:

the source terminals and/or the drain terminals of said first, second, and third FETs are biased via resistors in which one end is connected to the bias line; and

the source terminals and/or the drain terminals of said first, second, and third FETs are biased via resistors in which one end is connected to said bias line.

14. The semiconductor integrated circuit device according to claim 13, wherein

capacitance is connected between said bias line and said first and second ground regions, and the impedance of the capacitance is nearly 30% of the impedance of said resistor or less.