MOS random access memory having array of trench type one-capacitor/one-transistor memory cells

• US 5,731,609 A
• Filed: 02/24/1997
• Issued: 03/24/1998
• Est. Priority Date: 03/19/1992
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hamamoto, Takeshi, Horiguchi, Fumio
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/804,573
• Time in Patent Office: 393 Days
• Field of Search: 257/301, 257/302, 257/303, 257/305
• US Class Current: 257/302
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.

Claims

1. A random access memory comprising:

a semiconductor substrate having a plurality of trenches formed in a form of rows and columns on a main surface of said substrate;

a plurality of capacitors formed in lower portions of said trenches, respectively, each of said plurality of capacitors including a plate electrode composed of said semiconductor substrate, a capacitor insulating film formed thereon, a storage electrode formed on said capacitor insulation film and buried in each of said lower portions of said trenches;

a plurality of MOS transistors formed in upper portions of said trenches, respectively, each of said transistors including;

a channel formation region composed of a semiconductor film formed above a side surface of each of said upper portions of said trenches with a first insulating film interposed therebetween;

a gate electrode formed above said channel formation region with a gate insulation film interposed therebetween and insulatively buried in each of said upper portions of said trenches, said gate electrode being formed so as to continuously extend on said main surface of said substrate in a direction of said rows to serve as a word line;

a first impurity-doped region formed as said storage electrode and connected to a lower end of said channel formation region;

a second impurity-doped region formed, above said main surface of said substrate, beside said gate electrode and along one side of said word line; and

a plurality of bit lines each connected to said second impurity-doped region and formed continuously in a direction of said columns above said main surface of said substrate wherein said second-impurity doped region is shared by adjacent ones of said transistors arranged in the direction of said columns and is connected, exclusively when said gate electrode is supplied with an activation signal to make said channel formation region conductive, to an adjacent one of said second impurity-doped region through an upper end of said channel formation region interposed therebetween on said main surface of said substrate, thereby being continuously linked in the direction of said columns to be served as another bit line.

2. The memory according to claim 1, wherein said second impurity-doped region is shared by adjacent ones of said plurality of transistors arranged in the direction of said columns and each of said bit lines is connected to said second impurity-doped region shared by each two of said transistors.

3. The memory according to claim 1, wherein said second impurity-doped region is formed above said main surface of said substrate with a second insulating film interposed therebetween.

4. The memory according to claim 3, wherein a third insulating film is formed between said main surface of said substrate and said second insulating film under said second impurity-doped region.

5. The memory according to claim 1, wherein said second impurity-doped region is directly formed on said main surface of said substrate.

6. The memory according to claim 1, wherein adjacent transistors of said plurality of MOS transistors arranged in a direction of said bit lines share said second impurity-doped region with each other, thereby connecting said MOS transistors in series which include a plurality of second impurity-doped regions and each of said plurality of bit lines is connected to said plurality of second impurity-doped regions alternatively along the direction of said bit lines.