Power semiconductor devices having overlapping floating field plates for improving breakdown voltage capability

• US 5,731,627 A
• Filed: 02/26/1997
• Issued: 03/24/1998
• Est. Priority Date: 02/29/1996
• Status: Expired due to Term

• Current Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seok, Kyung-Wook
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/806,813
• Time in Patent Office: 391 Days
• Field of Search: 257/630, 257/638, 257/315, 257/448, 257/452
• US Class Current: 257/630
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith. To improve the breakdown characteristics of the P-N junction, an electrically insulating region is provided on the face and a primary field plate is formed on an upper surface of the electrically insulating region and in contact with the second region of second conductivity type. In addition, a first dielectric region (e.g., SiO₂) is provided on an upper surface of the electrically insulating region and on an upper surface of the primary field plate. A first floating field plate is formed on an upper surface of the electrically insulating region and on an upper surface of the first dielectric region extending opposite and overlapping the primary field plate. A second dielectric region is provided on the upper surface of the electrically insulating region and on an upper surface of the first floating field plate. A second floating field plate is also provided on the upper surface of the electrically insulating region and on an upper surface of the second dielectric region extending opposite and overlapping the first floating field plate.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first region of first conductivity type therein extending to a surface thereof;

a second region of second conductivity type in said first region and forming a P-N junction therewith;

an electrically insulating region on said first region at the surface of said substrate;

a primary field plate electrically connected to said second region and extending onto an upper surface of said electrically insulating region;

a first dielectric region on an upper surface of said primary field plate extending opposite said electrically insulating region;

a first floating field plate on the upper surface of said electrically insulating region and on an upper surface of said first dielectric region extending opposite said primary field plate;

a third region of second conductivity type in said first region of first conductivity type and forming a P-N junction therewith; and

a termination field plate electrically connected to said third region and capacitively coupled to said first floating field plate.

2. The power semiconductor device of claim 1, further comprising a second dielectric region on an upper surface of said first floating field plate extending opposite said electrically insulating region;

and a second floating field plate on the upper surface of said electrically insulating region and on an upper surface of said second dielectric region extending opposite said first floating field plate.

3. The power semiconductor device of claim 2, further comprising a third dielectric region on an upper surface of said second floating field plate extending opposite said electrically insulating region;

and wherein said termination field plate extends on an upper surface of said third dielectric region extending opposite said second floating field plate.

4. The power semiconductor device of claim 3, wherein a first capacitance between said first floating field plate and said primary field plate is greater than a second capacitance between said second floating field plate and said first floating field plate.

5. The power semiconductor device of claim 4, wherein the first capacitance is greater than about two times the second capacitance.

6. The power semiconductor device of claim 3, wherein a first capacitance between said first floating field plate and said primary field plate is greater than a second capacitance between said second floating field plate and said first floating field plate;

and wherein the second capacitance is greater than a third capacitance between said termination field plate and said second floating field plate.

7. The power semiconductor device of claim 6, wherein the first capacitance is greater than about two times the second capacitance and the second capacitance is greater than about two times the third capacitance.

8. The power semiconductor device of claim 3, wherein said first, second and third dielectric regions extend onto the upper surface of said electrically insulating region.

9. A semiconductor device having overlapping floating field plates, comprising:

a semiconductor substrate having a first region of first conductivity type therein extending to a surface thereof;

a second region of second conductivity type in said first region at the surface and forming a P-N junction therewith;

an electrically insulating region on said first region at the surface of said substrate;

a primary field plate electrically connected to said second region at the surface and extending onto an upper surface of said electrically insulating region;

a first dielectric region on an upper surface of said primary field plate extending opposite said electrically insulating region; and

a first floating field plate on the upper surface of said electrically insulating region and on an upper surface of said first dielectric region extending opposite said primary field plate.

10. The semiconductor device of claim 9, further comprising a second dielectric region on an upper surface of said first floating field plate extending opposite said electrically insulating region;

and a second floating field plate on the upper surface of said electrically insulating region and on an upper surface of said second dielectric region extending opposite said first floating field plate.

11. The semiconductor device of claim 10, wherein a first capacitance between said first floating field plate and said primary field plate is greater than a second capacitance between said second floating field plate and said first floating field plate.

12. The semiconductor device of claim 11, wherein the first capacitance is greater than about two times the second capacitance.