Off-chip driver circuit

• US 5,731,714 A
• Filed: 09/28/1995
• Issued: 03/24/1998
• Est. Priority Date: 09/29/1994
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Monk, Trevor, Dicke, Curtis
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/535,876
• Time in Patent Office: 908 Days
• Field of Search: 326/968, 326/80, 326/83, 327/108, 327/109
• US Class Current: 326/83
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Claims

1. An off-chip driver circuit having a first input terminal and an output terminal, the off-chip driver circuit comprising:

a pull-up transistor connected between a supply voltage and the output terminal, the pull-up transistor having a control terminal connected to the first input terminal;

an overshoot detection circuit connected to the output terminal, the overshoot detection circuit supplying at its output an overshoot signal when an overshoot voltage at the output terminal is detected; and

a clamping circuit connected between the first input terminal and a reference voltage, the clamping circuit having an input connected to the output of the overshoot detection circuit, the clamping circuit for clamping the first input terminal to the reference voltage.

2. The off-chip driver circuit according to claim 1 wherein the clamping circuit includes a clamping transistor having a control terminal for receiving the overshoot signal.

3. The off-chip driver circuit according to claim 2 wherein the clamping circuit further includes a switching transistor connected in series with the clamping transistor and having a control terminal for receiving a control signal to enable the clamping circuit.

4. The off-chip driver circuit according to claim 1, further comprising a pull-down transistor connected in series with the pull-up transistor, and having a control terminal connected to a second input terminal of the off-chip driver circuit, the common node between the pull-down transistor and the pull-up transistor defining the output terminal.

5. The off-chip driver circuit according to claim 1, further comprising a disable circuit connected to the clamping circuit and having a control terminal for receiving a disable signal to disable the clamping circuit of the off-chip driver.

6. The off-chip driver circuit according to claim 5 wherein the disable circuit includes:

a first transistor having a control terminal connected to a second input terminal of the off-chip driver circuit; and

a second transistor connected in series with the first transistor and having a control terminal for receiving the disable signal.

7. The off-chip driver circuit according to claim 1, further including a pass gate circuit connected between the first input terminal and the control terminal of the pull-up transistor.

8. The off-chip driver circuit according to claim 7, further including a control transistor connected between the control terminal of the pull-up transistor and the output terminal, the control transistor having a control terminal connected to a given potential.

9. The off-chip driver circuit according to claim 7, further including an auxiliary pass transistor connected between the first input terminal and the control terminal of the pull-up transistor.

10. An off-chip driver circuit having at least one input terminal and an output terminal, said off-chip driver circuit including:

a pull-up transistor connected between a supply voltage and the output terminal, the pull-up transistor having a control terminal connected to said at least one input terminal when the off-chip driver circuit is used in an output mode;

a clamping circuit including a clamping transistor having a controllable path connected between the first input terminal and a reference voltage and a control terminal connected to receive an overshoot signal; and

an overshoot detection transistor having a controllable path connected between said output terminal and an overshoot detection node, said overshoot detection node supplying said overshoot signal to said clamping transistor when an overshoot voltage on the output terminal is detected.

11. An off-chip driver circuit according to claim 10 wherein the clamping circuit comprises a switching transistor connected in series between said clamping transistor and said reference voltage and adapted to receive a control signal for enabling the clamping circuit.

12. An off-chip driver circuit according to claim 10 which comprises a pull-down transistor connected in series with said pull-up transistor between said supply voltage and said reference voltage, the output terminal being at a node between said pull-up and said pull-down transistors, a control terminal of said pull-down transistor being connected to a second input terminal of the off-chip driver circuit.

13. An off-chip driver circuit according to claim 10 which comprises a disable circuit operative in response to a disable signal to disable the clamping transistor.

14. An off-chip driver circuit according to claim 12 which comprises a disable circuit operative in response to a disable signal to disable the clamping transistor, wherein said disable circuit comprises a first transistor having a control terminal connected to the second input terminal of the off-chip driver circuit and a controllable path connected between the control terminal of the clamping transistor and a switch element.

15. An off-chip driver circuit according to claim 14 wherein said switch element comprises a transistor having a control terminal connected to receive said disable signal and a controllable path connected between said first transistor of the disable circuit and said reference voltage.

16. An off-chip driver circuit according to claim 10 which includes a pass gate connected between said at least one input terminal and the control terminal of the pull-up transistor.

17. An off-chip driver circuit according to claim 16 which comprises a control transistor having a controllable path connected between the control terminal of the pull-up transistor and the output terminal and a control terminal connected to a control potential.

18. An off-chip driver circuit according to claim 17 comprising an auxiliary pass transistor having a control terminal and a controllable path connected between a reference terminal and the control terminal of the pull-up transistor.

19. A driver circuit according to claim 18 wherein the pass gate comprises an isolation transistor of a first conductivity type and a transistor of a second conductivity type in parallel with said isolation transistor and having a control terminal connected to the supply voltage.

20. A driver circuit according to claim 19 wherein the pull-up transistor, control transistor, auxiliary pass transistor and detection transistor are p-channel transistors formed in a common n-well, said driver circuit including a further p-channel transistor for biasing said n-well and having a control terminal coupled to said output terminal.

21. An off-chip driver circuit having at least one input terminal and an output terminal, said off-chip driver circuit including:

a pull-up transistor connected between a supply voltage and the output terminal, the pull-up transistor having a control terminal connected to said at least one input terminal when the off-chip driver circuit is used in an output mode;

a clamping circuit including a clamping transistor having a controllable path connected between the first input terminal and a reference voltage and a control terminal connected to receive an overshoot signal;

an overshoot detection transistor having a controllable path connected between said output terminal and an overshoot detection node, said overshoot detection node supplying said overshoot signal to said clamping transistor when an overshoot voltage on the output terminal is detected; and

a pass gate connected between said at least one input terminal and the control terminal of the pull-up transistor.