Time-interleaved bit-plane, pulse-width-modulation digital display system
First Claim
1. A method of forming a plurality of pulse width modulating signals for delivery to a digital display having a plurality of rows and a plurality of columns, wherein the display is configured to receive the pulse width modulating signals a row of pixels at a time, the method comprising the steps of:
- a. receiving a predetermined number of bits for each signal, wherein the bits are sufficient for defining the signal, such that each one of the bits represents a different duration event;
b. storing the bits;
c. writing data to all the rows, one row at a time, the step of writing comprising selecting a collection of bits for each pixel in a row for forming a signal of a predetermined duration;
d. forming a plurality of signals, one for each of the collection of bits, of a duration representative of the collection of bits and coupling the signals to a predetermined one of the rows of the display; and
e. selecting a replacement collection of bits for any event that will expire at a next clock pulse wherein at least three consecutive collections of bits are displayed for a different duration.
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Accused Products
Abstract
A time interleaved bit addressed weighted pulse width modulation (PWM) method and apparatus reduces the bandwidth requirement necessary for providing a plurality of data entries regarding multiple points of information. As is well known, a weighted PWM scheme modulates an output by utilizing a frame time that is divided into events of varying durations; most conventional schemes have each bit in the frame being half the duration of its predecessor. The modulated signal is activated during all, some or none of the events in the frame to develop a signal representing a particular parameter. This method and apparatus can be used in a display for selecting among varying levels of gray scale or from among multiple colors on a palette. In one application for a display, a register containing the same number of data pits as pixels in a row of the display is provided. The register is loaded with one bit per frame for each pixel in the entire row. The bandwidth is reduced because the bit for each of the pixels are not all for the same weight event. This allows a bit for a long duration event to be displayed in one pixel, while more than one bit for shorter duration events to be displayed in another pixel. This obviates the need to load one bit for each pixel in the row during the shortest event duration. The organization of the sequence of the events amongst the various rows can be pseudo-random to achieve reduced bandwidth. If the organization is pseudo-random the order can be pre-selected for an optimized bandwidth or organized into a predetermined format to achieve a pseudo-random effect.
201 Citations
27 Claims
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1. A method of forming a plurality of pulse width modulating signals for delivery to a digital display having a plurality of rows and a plurality of columns, wherein the display is configured to receive the pulse width modulating signals a row of pixels at a time, the method comprising the steps of:
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a. receiving a predetermined number of bits for each signal, wherein the bits are sufficient for defining the signal, such that each one of the bits represents a different duration event; b. storing the bits; c. writing data to all the rows, one row at a time, the step of writing comprising selecting a collection of bits for each pixel in a row for forming a signal of a predetermined duration; d. forming a plurality of signals, one for each of the collection of bits, of a duration representative of the collection of bits and coupling the signals to a predetermined one of the rows of the display; and e. selecting a replacement collection of bits for any event that will expire at a next clock pulse wherein at least three consecutive collections of bits are displayed for a different duration.
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2. An apparatus for providing an n-bit weighted pulse width modulation to each of m signal lines wherein each signal line is configured to received n signals for displaying bits of varying duration having a shortest duration to a longest duration, which are representative of m×
- n pulse width modulated data bits, comprising a control circuit for selecting a first collection of data bits each representing a varying duration, for forming a corresponding first collection of signals for displaying a predetermined row of bits for a predetermined duration, and for subsequently displaying in remaining rows, subsequent collections of bits wherein at least three consecutive collections are for bits of different duration.
- View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An apparatus for providing weighted pulse width modulation to each of a plurality of signals within a frame time, comprising:
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a. a memory for storing a plurality of collection of data bits representative of each of the signals wherein each of the collections comprises a like number of bits such that each bit in a collection represents one of a predetermined different event duration; b. a selecting circuit for selecting from a first subset of the plurality one bit per collection forming a first set of selected bits all having a predetermined event duration; and c. a circuit for generating a plurality of modulated signals corresponding to the selected bits; and d. a control circuit for controlling the selecting circuit to select from a second subset of the plurality one bit per collection forming a second set of selected bits such that only those bits are replaced during a next clock cycle for which the different event duration will expire at a next clock pulse and further wherein only one set of bits can expire at any one clock pulse. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A display comprising:
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a. an array of pixels arranged in a plurality of rows and a plurality of columns; b. a register having a plurality of storage elements for temporarily storing data, the register having as many storage elements as pixels in a row; c. a control circuit coupled to the memory and to the register for controlling a transfer of the data into a predetermined one of the rows; d. a memory for storing a collection of bits for each of the pixels wherein each of the collections comprises a like number of bits such that each bit in a collection represents one of a predetermined different event duration; and e. a selection circuit for selecting one bit per row forming a set of selected bits having a predetermined event duration, and then for a different row selecting a new set of selected bits such that only those bits are replaced for which the different event duration has expired. - View Dependent Claims (25, 26)
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27. A method of forming a plurality of pulse width modulating signals comprising the steps of:
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a. storing a predetermined number of bits for each signal, wherein the bits are sufficient for defining the signal, such that each one of the bits represents a different duration event; b. selecting a collection of bits, one for each signal, such that bits for at least two different duration events are selected; and c. selecting a replacement bit for any event that will expire at a next clock pulse.
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Specification
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- Resources
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Current AssigneeSilicon Light Machines Corporation (SCREEN Holdings Co., Ltd.)
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Original AssigneeSilicon Light Machines Corporation (SCREEN Holdings Co., Ltd.)
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InventorsStraker, Bryan P., Alioshin, Paul A., Aras, Richard John Edward
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Primary Examiner(s)Tung, Kee M.
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Assistant Examiner(s)Kovalick, Vincent E.
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Application NumberUS08/635,479Time in Patent Office701 DaysField of Search345/84, 345/87, 345/89, 345/98, 345/112, 345/147, 345/148, 345/150, 345/185, 345/197US Class Current345/692CPC Class CodesG09G 2310/0216 Interleaved control phases ...G09G 3/2022 using sub-frames
