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Chip sizing for hierarchical designs

  • US 5,731,985 A
  • Filed: 04/23/1996
  • Issued: 03/24/1998
  • Est. Priority Date: 04/23/1996
  • Status: Expired due to Fees
First Claim
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1. A method of apportioning increased area of a parent cell to child macro cells of a hierarchical integrated circuit design, comprising the steps of:

  • a) determining parent growth factors in X and Y directions for the parent cell;

    b) determining child growth factors in X and Y directions for the child cell according to a geometric progression based on the growth factors of the parent cell.

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