Non-volatile semiconductor memory device

• US 5,732,022 A
• Filed: 03/06/1997
• Issued: 03/24/1998
• Est. Priority Date: 03/31/1992
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugiura, Nobutake, Kato, Hideo, Asano, Masamichi, Uchigane, Kiyotaka
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/812,765
• Time in Patent Office: 383 Days
• Field of Search: 365/185.24, 365/185.18, 365/185.22, 365/185.29, 365/185.23, 365/185.3, 365/201, 365/218
• US Class Current: 365/185.24
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

Claims

1. A non-volatile semiconductor memory device, comprising:

a memory cell array composed of a plurality of electrically data writable and erasable non-volatile memory cells arranged in a matrix pattern, each of the memory cells being a transistor having a source, a drain, a floating gate and a control gate;

data being written in each memory cell by injecting electrons into the floating gate thereof and erased from each memory cell by extracting electrons from the floating gate thereof;

said drain of each memory cell being connected to a bit-line which receives data from the memory cell, a test of data erasure being achieved by checking whether the source-drain can be turned on or not when a predetermined voltage is kept applied to the control gate, turning on or not of said memory cell being checked based on the potential of the bit-line, the bit-line being connected to an I/O pad when the test of data erasure is achieved so that the potential of the bit-line may be measured external to the memory device; and

a source bias circuit for applying a positive bias voltage to the sources of the memory cells to be tested in the erasure test, to shift each threshold value of each memory cell in a forward direction thereof, said positive bias voltage being a variable voltage that is externally applied to the memory device.

2. The non-volatile semiconductor memory device of claim 1, wherein the respective control gates of the memory cells arranged in a row are connected in common to a word line corresponding to the row, and the respective drains of the memory cells arranged in a column are connected in common to bit line line corresponding to the column.

3. The non-volatile semiconductor memory device of claim 1, which further comprises:

a row decoder circuit for selecting any of the word lines; and

a column decoder circuit for selecting any of the bit lines to connect the selected bit line to a test line having a first test terminal for applying a test voltage, the threshold value of the memory cells being tested by checking whether a potential on the test line is lowered or not when the memory cells no be tested are turned on or off during a condition in which the test voltage is applied to the first test terminal to keep the nest line at the potential.

4. The non-volatile semiconductor memory device of claim 3, which further comprises:

a first switch connected between the test line and the first test terminal;

a second switch connected to the test line; and

a sense amplifier circuit connected to the test line via said second switch, said first and second switches being turned on or off in test.

5. The non-volatile semiconductor memory device of claim 4, wherein said row decoder circuit comprises final stage buffers each having first and second transistors connected in series between a high voltage supply and a low voltage supply, an intermediate point of both the first and second transistors being connected to the corresponding word line to apply a voltage to the word line, the applied voltage being lower than the high supply voltage by a threshold voltage of said first transistor.

6. The non-volatile semiconductor memory device of claim 5, wherein said first transistor of each of said final stage buffers is a P-channel transistor and said second transistor thereof is an N-channel transistor.

7. The non-volatile semiconductor memory device of claim 6, wherein any one of a first circuit operating high supply voltage and a second data writing high supply voltage higher than the first supply voltage are selectively applied as the high supply voltage.

8. The non-volatile semiconductor memory device of claim 7, wherein said source bias circuit comprises:

a third test terminal for receiving a test signal external to the semiconductor device; and

an internal circuit for outputting the bias voltage to the memory cells to be tested, in response to the test signal.

9. The non-volatile semiconductor memory device of claim 8, wherein the sources of all the memory cells are connected to one common source.

10. The non-volatile semiconductor memory device of claim 9, wherein said source bias circuit comprises:

a positive side voltage supply for supplying the bias voltage to the common source; and

a feedback circuit for adjusting the bias voltage by boosting and deboosting the bias voltage to and below a predetermined value.

11. The non-volatile semiconductor memory device of claim 10, wherein the common source is connected to the positive side voltage supply via a fifth switch and to the low voltage supply via a sixth switch, said fifth and sixth switches being turned on and off, respectively in test.

12. The non-volatile semiconductor memory device of claim 1, wherein said source bias circuit comprises:

a third test terminal for receiving a test signal external to the semiconductor device; and

an internal circuit for outputting the bias voltage to the memory cells to be tested, in response to the test signal.

13. The non-volatile semiconductor memory device of claim 12, wherein the sources of all the memory cells are connected to one common source.

14. The non-volatile semiconductor memory device of claim 13, wherein said source bias circuit comprises:

a positive side voltage supply for supplying the bias voltage to the common source; and

a feedback circuit for adjusting the bias voltage by boosting and deboosting the bias voltage to and below a predetermined value.

15. The non-volatile semiconductor memory device of claim 14, wherein the common source is connected to the positive side voltage supply via a sixth switch, said fifth and sixth switches being turned on and off, respectively in test.