Memory having selectable output strength

• US 5,732,027 A
• Filed: 12/30/1996
• Issued: 03/24/1998
• Est. Priority Date: 12/30/1996
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Arcoleo, Mathew R., Leong, Raymond M., Johnson, Derek R.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/777,488
• Time in Patent Office: 449 Days
• Field of Search: 365/189.05, 365/189.07, 365/230.06, 365/191
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device. Since the output buffer circuit of the invention allows the output buffer drive strength to be more closely tailored to the electrical load being driven, signal reflections, voltage overshoot and undershoot, and timing problems that can result from mismatch between the output buffer drive strength and the associated electrical load can be reduced.

Claims

1. An output buffer circuit having an input node adapted to receive an input signal and an output node adapted to provide an output signal, comprising:

means for producing an output signal in response to a received input signal from a memory cell, the means for producing further comprising;

first current control means for providing current to or from the output node in response to the received input signal; and

second current control means for providing current to or from the output node in response to the received input signal, the first and second current control means being connected or connectable in parallel between the input node and output node; and

means for selectably controlling current flow through the means for producing to thereby control and/or select the output signal, the means for selectably controlling further comprising means for operably connecting the first and/or second current control means to the input and output nodes in response to a control signal to enable the operably connected current control means to provide current to the output node.

2. An output buffer circuit as in claim 1, wherein each of the first and second current control means comprises an inverter.

3. An output buffer circuit as in claim 2, wherein each of the inverters of the first and second current control means comprises an N-channel transistor and a P-channel transistor connected in series between a supply voltage and a ground voltage.

4. An output buffer circuit as in claim 3, wherein the means for operably connecting the first and/or second current control means to the input and output nodes in response to a control signal comprises:

a first switching transistor connected in series with the N-channel transistor of the first or second current control means between the output node and the ground voltage; and

a second switching transistor connected in series with the corresponding P-channel transistor of the first or second current control means between the output node and the supply voltage.

5. A system for selectably controlling the drive strength of an output buffer, comprising:

a memory cell;

an output buffer circuit adapted to receive an input signal from the memory cell and to provide an output signal, comprising;

means for producing the output signal in response to the received input signal; and

means for selectably controlling the current flow through the means for producing the output signal; and

means for operating the means for selectably controlling in accordance with a control signal.

6. A system as in claim 5, further comprising means for generating a control signal.

7. A system as in claim 6, wherein the means for generating a control signal comprises means for establishing a voltage of predetermined magnitude.

8. A system as in claim 7, wherein the means for establishing a voltage of predetermined magnitude further comprises a resistor configured to couple a predetermined voltage to the means for selectably controlling.

9. A system as in claim 6, wherein:

the means for generating a control signal comprises means for generating a series of signals at a predetermined time; and

the system further comprises means for storing data representing the series of signals.

10. A system as in claim 6, wherein:

the means for generating a control signal comprises means for generating a series of uniquely identifiable signals; and

the system further comprises means for storing data representing the series of signals.