Semiconductor memory
DCFirst Claim
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1. A semiconductor memory comprising:
- a pair of data lines which are formed substantially in parallel to each other;
a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;
a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said data lines;
an amplifier having a pair of N-channel MOS transistors and a pair of P-channel MOS transistors, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistor has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, and wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines, wherein said amplifier provides said data lines with a high-level potential and a low-level potential, respectively; and
a first switching MOS transistor having a source-drain path provided between said pair of data lines, wherein said first switching MOS transistor sets said pair of data lines at an intermediate level between said high-level potential and said low-level potential when said plurality of memory cells are in a non-selected state.
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Abstract
A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
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Citations
6 Claims
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1. A semiconductor memory comprising:
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a pair of data lines which are formed substantially in parallel to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines; a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said data lines; an amplifier having a pair of N-channel MOS transistors and a pair of P-channel MOS transistors, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistor has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, and wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines, wherein said amplifier provides said data lines with a high-level potential and a low-level potential, respectively; and a first switching MOS transistor having a source-drain path provided between said pair of data lines, wherein said first switching MOS transistor sets said pair of data lines at an intermediate level between said high-level potential and said low-level potential when said plurality of memory cells are in a non-selected state. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification