System and method for multi-frame received queuing with sorting in an asynchronous transfer mode (ATM) system

• US 5,732,082 A
• Filed: 08/11/1995
• Issued: 03/24/1998
• Est. Priority Date: 08/11/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wartski, Mark Crane, Schroter, Russell Evan, Lee, Joseph Kinman
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Carman, Melissa Kay
• Application Number:
  US08/513,706
• Time in Patent Office: 956 Days
• Field of Search: 370/395, 370/399, 370/474, 370/419, 370/428, 370/374, 370/398, 370/412, 370/455
• US Class Current: 370/395.6
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An ATM information system processes information at the frame level using a processor including a device driver; a system memory and an adapter for sorting data cells into partially completed frames stored in the system memory using control information provided by the device driver. A controller in the adapter determines when an end of frame indication is received in a cell and updates a pointer in system memory for a completed frame list to a recently completed frame. The device driver processes frames in a completed frame list according a priority of the list. The device driver processing is independent of the sorting and storing of completed frames received in the system memory which improves the performance of the driver and the ability to handle delay sensitive traffic.

Claims

1. An information system including a system processor with memory and an adapter for receiving data cells and reassembling the cells into sorted prioritized frames in system memory whereby the system can process information at the frame level comprising:

means for supplying to the adapter virtual circuit control information including prioritized frame sort information for a plurality of data sources;

means for receiving and sorting cells into partially completed ATM frames in a first area of the system memory according to the virtual circuit control information;

means for determining when an end of frame indication is received in a cell;

means for linking completed frames onto one of a plurality of received ready lists in a second separate area of the system memory according to a priority of the list;

means for updating a pointer in the system memory for a prioritized completed frame list through a most recently completed frame; and

means for serving the data sources with frames according to the highest priority data source.

2. The system of claim 1 wherein data cells are stored in system memory in partially completed frames according to the virtual circuit control information until a frame is complete whereupon the completed frame is linked in system memory to a received ready list for the most recently completed frame according to the virtual circuit control information.

3. The system of claim 2 wherein the system memory includes a plurality of received ready lists of frames prioritized according to the virtual circuit control information.

4. The system of claim 3 wherein data cells are reassembled into data frames while the system processor performs other functions.

5. The system of claim 4 further including a device driver in the system processor for supplying virtual circuit control information to the means for supplying virtual circuit control information to the adapter.

6. The system of claim 5 further including controller means for reading the virtual circuit control information to transfer a data cell into system memory.

7. The system of claim 6 further including interrupt means which when set by the controller means notifies the device driver that a recently completed frame in system memory is linked to a received ready list.

8. The system of claim 7 wherein the controller means writes into a virtual circuit control information register a pointer indicating an address of the most recently completed frame system memory address.

9. An ATM information system for processing and prioritizing data at the frame level comprising:

a system processor and a system memory

an adapter for receiving data cells from an ATM unit and sorting the data cells into partially completed ATM frames for storage in a first area of the system memory;

said adapter including further means providing control information to a controller for linking completed ATM frames on one of a plurality of prioritized received ready lists for storage in a second separate area of the system memory according to a priority of a data source supplying the data cells;

said controller means further responsive to the control information to obtain a pointer to most recently completed ATM frame for each prioritized received ready list; and

means for generating an interrupt when a frame has been added to a received ready list notifying the system processor for processing data at the frame level.

10. The information system of claim further including means for exchanging virtual circuit information with the controller.

11. The information system of claim wherein the controller controls a cell buffer to capture data cells for transfer to the system memory.

12. The information system of claim 11 where the controller receives information from a control register with respect to the storage of data frames on received ready lists and writes information to the control register indicating the address of most recently completed frames in a received ready list.

13. The information system of claim 12 further including a received ready list interrupt register for notifying the system processor when a completed frame has been linked to a received ready list.

14. The information system of claim 13 wherein the system memory links completed ATM frames on received ready list according to priority of a data source associated with the received ready list.

15. The information system of claim 14 wherein the adapter includes addresses for storing partially completed ATM frames.

16. In an ATM information system including a system processor having a device driver and a system memory coupled to an adapter including a cell buffer, a frame controller, a virtual circuit control information register and an interrupt register, a method for processing data cells onto prioritized frame levels comprising the steps of;

a) writing virtual circuit control information into the virtual circuit control register using the device driver to indicate one of a plurality of prioritized receive ready lists for linking completed frames in system memory;

b) monitoring the data cells from a communication network for processing by the system;

a "no" condition continuing the monitoring of the network;

a "yes" condition moving the data cell from the network into the cell buffer;

c) transferring the data cell from the cell buffer across a system interface into a partially completed frames storage area in the system memory using the frame controller;

d) monitoring the cell buffer for an end of frame indication in a data cell;

a "no" condition repeating steps a, b, and c;

a "yes" condition activating the frame controller to read virtual circuit control information to determine one of the prioritized received ready list to link completed frames;

e) linking completed ATM frames in a completed frame storage area in the system memory to the most recently prioritized received ready list system address specified by the virtual circuit control information using the frame controller;

f) updating the virtual circuit control information with a completed frame system memory address using the frame controller; and

g) notifying the device driver by setting a appropriate received ready list interrupt for completed frames using the frame controller to activate the interrupt register.

17. The method of claim 16 further including the step of obtaining the received ready list forward pointer system address specified by the virtual circuit control information using the frame controller.

18. The method of claim 16 further including the step of writing received ready list forward pointer system address to point to the most recently completed frame in system memory using the frame controller.