Frequency error compensation for direct sequence spread spectrum systems

• US 5,732,111 A
• Filed: 12/06/1995
• Issued: 03/24/1998
• Est. Priority Date: 12/06/1995
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: Rockwell International Corporation
• Inventors: Walley, John S.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): WEBSTER, BRYAN E
• Application Number:
  US08/568,095
• Time in Patent Office: 839 Days
• Field of Search: 375/200, 375/206, 375/316, 375/340, 375/344, 455/192.1, 455/192.2
• US Class Current: 375/344
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0095 in a preamble or similar structure
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier

Abstract

A frequency error calibration, estimation and compensation device and method for direct sequence spread spectrum systems, such as digital cordless telephones having a handset and a base station. Initial frequency calibration occurs when the handset is physically coupled to the base station. The allowable frequency error range is divided into a plurality of frequency bins. Both the handset and base station transmit and receive messages using a predetermined frequency offset bin as an estimate of the frequency error. A signal quality value is determined and then a next bin is selected and a next signal quality value is determined. Once a signal quality value has been determined for each frequency bin, a communications link is established between the handset and the base station to allow automatic frequency control tracking to fine tune the frequency offset value. If the signal quality is not above a threshold value, the procedure is repeated. After system calibration, frequency error estimation is performed by cross product demodulation of the received in-phase and quadrature signals. The cross product output is limited and filtered. A phase rotator performs frequency compensation by multiplying the received in-phase and quadrature signals by (cosφ(t)+jsinφ(t)) where φ(t) is the sum of the current phase value and the limited and filtered cross product value.

Claims

1. In a direct sequence spread spectrum communications system, a frequency error estimation and compensation circuit to correct frequency error in received in-phase (I) and quadrature (Q) signals comprising:

matched filter means for removing a spreading code from the received I and Q signals;

phase rotator means for multiplying the received I and Q signals by (cosφ

(t)+jsinφ

(t)) before providing the received I and Q signals to the matched filter means, wherein φ

(t) is a phase value representing the estimated frequency error in the received I and Q signals and wherein an initial phase value φ

(t) for the phase rotator means is determined by a frequency calibration bin search;

cross product determining means for calculating a cross product of the received I and Q signals, the cross product an estimate of the frequency error in the received I and Q signals; and

filtering means for filtering and limiting the cross product, and determining a phase error value based on the filtered and limited cross product, the phase error value being used to modify the phase value φ

(t);

wherein the phase rotator means adjusts the phase of the received I and Q signals based on an updated phase value φ

(t) determined by adding a previous value φ

(t) with the phase error value determined by the filtering means.

2. The frequency error estimation and compensation circuit of claim 1 wherein the phase rotator means comprises:

rectangular to polar conversion means for converting the received I and Q signals from rectangular form to polar form, wherein the polar form of the I and Q signals comprise a Magnitude component and a Phase component;

phase rotator accumulator means for storing the phase value φ

(t);

first adder means for adding the phase value φ

(t) stored in the phase rotator accumulator means with the Phase component of the received I and Q signals and outputting a Modified Phase component;

second adder means for adding the phase value φ

(t) stored in the phase rotator accumulator means with the phase error value determined by the filtering means, wherein the output of the second adder means is then stored in the phase rotator accumulator means; and

polar to rectangular conversion means for converting the Magnitude component and the Modified Phase component to rectangular form.

3. The frequency error estimation and compensation circuit of claim 2 wherein the cross product determining means comprises:

delay means for delaying a current I and current Q signal by one bit time;

multiplying means for multiplying a current I signal value by a Q signal value delayed one bit time by the delay means, and outputting a first value, and for multiplying a current Q signal value by an I signal value delayed one bit time by the delay means, and outputting a second value;

subtractor means for subtracting the second value from the first value and outputting the cross product.

4. The frequency error estimation and compensation circuit of claim 3 wherein the filtering means comprises:

multiplier means for multiplying the cross product by a dot product demodulated received data value and outputting a scaled cross product; and

limiter means for limiting the scaled cross product value to one of -1,0 and +1, wherein the cross product is limited to -1 if the cross product calculated by the cross product determining means is less than 0, the cross product is limited to 0 is the cross product calculated by the cross product determining means equals 0, and the cross product is limited to +1 is the cross product calculated by the cross product determining means is greater than 0.

5. The frequency error estimation and compensation circuit of claim 4 wherein the filtering means further comprises:

n bit accumulator means for storing a n bit value;

m bit scale value storage means for storing a m bit programmable value;

n bit adder means for adding the value stored in the n bit accumulator means with the m bit value stored in the m bit scale value storage means, wherein when the adder means has an overflow, the phase error value is incremented when the overflow is positive and the phase error value is decremented when the overflow is negative, and wherein the n bit accumulator is reset to 0 when an overflow occurs.

6. The frequency error estimation and compensation circuit of claim 5 wherein n equals 6 and m equals 3.

7. In a digital cordless telephone system using direct sequence spread spectrum modulation having a handset and a base station, an automatic frequency control tracking circuit in both the handset and base station comprising:

analog to digital converter means for converting analog received in-phase (I) and quadrature (Q) signals into digital signals;

phase rotator means for multiplying the digital I and Q signals from the analog to digital converter means by (cosφ

(t)+jsinφ

(t)), wherein φ

(t) is a phase value representing the estimated frequency error in the received I and Q signals, the phase rotator means comprising;

rectangular to polar conversion means for converting the received I and Q signals from rectangular form to polar form, wherein the polar form of the I and Q signals comprise a Magnitude component and a Phase component;

phase rotator accumulator means for storing the phase value φ

(t);

first adder means for adding the phase value φ

(t) stored in the phase rotator accumulator means with the Phase component of the received I and Q signals and outputting a Modified Phase component;

second adder means for adding the phase value φ

(t) stored in the phase rotator accumulator means with a phase error value determined by a filtering means, wherein the output of the second adder means is then stored in the phase rotator accumulator means; and

polar to rectangular conversion means for converting the Magnitude component and the Modified Phase component to rectangular form;

matched filter means for removing a spread spectrum code sequence form the received I and Q signals;

cross product determining means for calculating a cross product of the received I and Q signals, the cross product being an estimate of the frequency error in the received I and Q signals, the cross product determining means comprising;

delay buffer means for delaying a current I and current Q signal by one bit time;

multiplying means for multiplying a current I signal value by a Q signal value delayed one bit time by the delay buffer means, and outputting a first value, and for multiplying a current Q signal value by an I signal value delayed one bit time by the delay buffer means, and outputting a second value;

subtractor means for subtracting the second value from the first value and outputting the cross product; and

filtering means for filtering and limiting the cross product, and determining a phase error value based on the filtered and limited cross product, the phase error value being used to modify the phase value φ

(t);

multiplier means for multiplying the cross product by a dot product demodulated received data value and outputting a scaled cross product;

limiter means for limiting the scaled cross product value to one of -1, 0 and +1, wherein the cross product is limited to -1 if the cross product calculated by the cross product determining means is less than 0, the cross product is limited to 0 is the cross product calculated by the cross product determining means equals 0, and the cross product is limited to +1 is the cross product calculated by the cross product determining means is greater than 0;

n bit accumulator means for storing a n bit value;

m bit scale value storage means for storing a m bit programmable value;

n bit adder means for adding the value stored in the n bit accumulator means with the m bit value stored in the m bit scale value storage means, wherein when the adder means has an overflow, the phase error value is incremented when the overflow is positive and the phase error value is decremented when the overflow is negative, and wherein the n bit accumulator is reset to 0 on an overflow;

wherein the phase rotator means adjusts the phase of the received I and Q signals from the analog to digital converter means using an updated phase value φ

(t) determined by the output of the second adder means.

8. The automatic frequency control tracking circuit of claim 7 wherein the n bit accumulator is a 6 bit accumulator.

9. The automatic frequency control tracking circuit of claim 7 wherein the phase rotator accumulator means stores an initial phase value φ

(t) determined by a frequency bin search performed during a system frequency error calibration.

10. The automatic frequency control tracking circuit of claim 7 wherein the filtering means further comprises a programmable gain control means to scale the limited cross product.