Self-testing multi-processor die with internal compare points

• US 5,732,209 A
• Filed: 05/14/1996
• Issued: 03/24/1998
• Est. Priority Date: 11/29/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Exponential Technology, Inc.
• Inventors: Lederer, Louis S., Blomgren, James S., Vigil, Peter J.
• Primary Examiner(s): Nguyen, Hoa T.
• Assistant Examiner(s): Elmore, Stephen C.
• Application Number:
  US08/649,117
• Time in Patent Office: 679 Days
• Field of Search: 364/488, 364/490, 364/228.3, 395/183.06, 395/182.09, 326/9, 326/10, 371/22.31, 371/22.34, 371/49.1
• US Class Current: 714/30
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU'"'"'s. When 3 CPU'"'"'s are on the die, their outputs are compared during a self-testing mode. If outputs from all three CPU'"'"'s match, then no error is detected. When two CPU'"'"'s outputs match, but a third CPU'"'"'s output mismatches, then the third CPU is faulty. The output compared from each CPU is a serial scan-chain shift-out, parity from internal test points, and a result written to the shared cache. Each CPU core has a serial scan chain. The serial scan chain strings together most flip-flops in the CPU core into a serial chain. A test clock is pulsed to shift out the data from these flip-flops. During each test clock period, the serial data from each CPU is compared to the serial data from other CPU'"'"'s. Internal test points within each CPU core are defined at high traffic areas in the pipeline. Parity is generated from these internal test points, and the parity from one CPU is compared to that for other CPU'"'"'s during each CPU clock cycle. The results from each CPU core written back to the shared cache are also compared, and arbitration allows one CPU to write the result to the shared cache while results from other CPU'"'"'s are discarded. A self-test circuit on the die accumulates errors for each CPU and reports these errors to an inexpensive external tester.

Claims

1. A self-testing microprocessor die comprising:

a first central processing unit (CPU) core, the first CPU core having a pipeline for processing a plurality of general-purpose instructions;

a second CPU core having a pipeline for processing the plurality of general-purpose instructions, the second CPU core substantially identical in function to the first CPU core;

a third CPU core having a pipeline for processing the plurality of general-purpose instructions, the third CPU core substantially identical in function to the first CPU core;

a shared cache, coupled to supply instructions and operands to the first CPU core, the second CPU core, and the third CPU core, the shared cache further coupled to I/O pins on the self-testing microprocessor die;

a self-test controller, receiving a first output from the first CPU core, a second output from the second CPU core, and a third output from the third CPU core, for comparing the first output, the second output, and the third output;

error signaling means, coupled to the self-test controller, for signaling a first error in the first CPU core when the first output does not match the second and third outputs, for signaling a second error in the second CPU core when the second output does not match the first and third outputs, and for signaling a third error in the third CPU core when the third output does not match the first and second outputs; and

error output means, coupled to the error signaling means, for applying to the I/O pins of the self-testing microprocessor die signals indicating the first, second, and third errors;

wherein the first, second, and third outputs are not applied to the I/O pins of the self-testing microprocessor die, an external tester not receiving or comparing the first, second, and third outputs from each CPU core, the external tester merely reading the first, second, and third errors from the error signaling means,

whereby outputs from different CPU cores are compared on-chip for signaling an error.

2. The self-testing microprocessor die of claim 1 wherein the first, second, and third outputs each comprise result data generated by processing of a general-purpose instruction in the pipeline, the result data being written to the shared cache,

whereby results written back to the shared cache from different CPU cores are compared for self-test.

3. The self-testing microprocessor die of claim 2 further comprising:

a self-test ROM, coupled to the shared cache, for permanently storing a test program comprising a sequence of general-purpose instructions, the test program executing an extensive variety of operations performed by each CPU core for testing functionality of each CPU core,

test activation means, coupled to an I/O pin on the self-testing microprocessor die, for activating a self-test mode and causing the test program from the self-test ROM to simultaneously begin executing on each of the CPU cores,

wherein external test vectors containing the test program are not applied to the I/O pins of the self-testing microprocessor die, the external test vectors merely activating the self-test mode to execute the test program from the self-test ROM.

4. The self-testing microprocessor die of claim 3 further comprising:

an arbitration unit, receiving simultaneous requests from the first, second, and third CPU cores to write the result data to the shared cache, the arbitration unit sending a grant acknowledgment to all three CPU cores indicating that their result data is being written to the shared cache, but the arbitration unit discarding the result data from two of the cores and writing the result data from a selected CPU core to the shared cache,

wherein the result data from the selected CPU core matches the result data from another CPU core,

whereby faulty write data that mismatches is not written to the shared cache.

5. The self-testing microprocessor die of claim 1 wherein the first, second, and third outputs each comprise a shift-out output, each CPU core further comprising a serial scan chain of flip-flops within each CPU core, the serial scan chain for serially shifting data in the flip-flops out to the shift-out output;

whereby serial scan chains from different CPU cores are compared for self-test.

6. The self-testing microprocessor die of claim 5 further comprising:

shift-clock means, coupled to the serial scan chain in each CPU core, for shifting bits of data in the serial scan chains out of the CPU core to the shift-out output, the bits of data in the serial scan chains being shifted by one bit for each pulse of a serial clock.

7. The self-testing microprocessor die of claim 1 wherein the first, second, and third outputs each comprise a plurality of internal test points within each CPU core, the internal test points being inaccessible from the I/O pins of the self-testing microprocessor die,

whereby internal test points from different CPU cores are compared for self-test.

8. The self-testing microprocessor die of claim 7 wherein the internal test points are compressed before being transmitted to the self-test controller.

9. The self-testing microprocessor die of claim 8 wherein the internal test points are compressed by generating parity bits for the internal test points, the parity bits being transmitted to the self-test controller for comparison.

10. The self-testing microprocessor die of claim 9 wherein the parity bits from the internal test points are generated and transmitted to the self-test controller each cycle of a CPU clock, the CPU clock for advancing instructions to a next pipeline stage in the pipeline in each CPU core,

whereby parity bits are generated from the internal test points and compared each CPU clock cycle.

11. The self-testing microprocessor die of claim 10 wherein the pipeline in each CPU core comprises an instruction pointer, a register file, and a plurality of pipeline stages including a decode stage for decoding general-purpose instructions, an address generate stage for generating an address of a data operand in the shared cache, an execute stage for performing an operation defined by a general-purpose instruction, and a write-back stage for writing a result to the register file, the internal test points comprising:

a first test point receiving an instruction address from the instruction pointer;

a second test point receiving an instruction ready for decoding by the decode stage;

a third test point receiving a data operand being written from the write-back stage to the register file;

whereby high-traffic test points deep within the pipeline are the internal test points compared by the self-test controller.

12. The self-testing microprocessor die of claim 11 wherein each CPU core further comprises a local cache, coupled to the shared cache, for storing instructions and operands for use by a local CPU core, the internal test points further comprising:

a fourth test point receiving a data operand being written to the local cache.

13. A method for testing a microprocessor die comprising the steps of:

connecting an external tester to external pins on the die;

asserting with the external tester an external test pin on the die to initiate a self-test mode by the die;

simultaneously resetting a plurality of substantially-identical processor cores on the die in response to the external test pin;

(a) pulsing a processor clock to the processor cores, the processor cores each generating an output which is not applied to external pins of the die;

(b) comparing the output generated from each processor core and signaling an error when at least one of the processor cores does not match the output from the other processor cores;

(c) setting an error bit for the processor core having the output that does not match the outputs from the other processor cores;

fetching additional instructions and repeating steps (a) to (c) until a test sequence is complete;

applying the error bits for each processor core to external pins on the die;

reading with the external tester the error bits for each processor core and marking the die as functional or non-functional in response to the error bits read;

whereby the die is self-tested by internally comparing outputs from multiple processor cores.

14. The method of claim 13 further comprising the step of:

testing a shared cache coupled to the processor cores;

loading instructions in the test sequence from a ROM on the die to the shared cache for fetching to the processor cores;

wherein the test sequence is stored in the ROM on the die and the test sequence is not supplied from the external tester.

15. The method of claim 14 wherein the output from each processor core comprises a result written to the shared cache.

16. The method of claim 15 wherein the output from each processor core further comprises parity bits generated from internal test points within each processor core, the internal test points not being accessible from the external pins of the die.

17. The method of claim 16 further comprising the steps of:

halting the pulsing of the processor clock;

(j) pulsing a test clock to flip-flops in each processor core connected together in a serial scan chain and shifting contents of the flip-flops down the serial scan chain;

(k) shifting out of a last flip-flop in the serial scan chain a shift output;

(l) comparing the shift output from each processor core;

(m) signaling an error when at least one of the processor cores does not match the shift output from the other processor cores;

(n) setting an error bit for the processor core having the shift output that does not match the shift outputs from the other processor cores;

repeating steps (j) through (n) until all the contents of the flip-flops in the serial scan chains have been shifted out through the shift output;

resuming the pulsing of the processor clock and continuing with step (a), whereby serial scan chains for each processor core are compared internally without an external comparison of the scan chains by the external tester.

18. The method of claim 17 wherein the external tester is a simple burn-in socket, the method further comprising the step of:

continuously repeating the test sequence at an elevated temperature and applying the error bits for each processor core to external pins on the die,

whereby the test sequence is repeated continuously to exercise the die for burn-in.

19. A multi-processor die comprising:

a plurality of central processing unit (CPU) cores, each core having a pipeline for processing instructions and a scan test chain serially connecting storage nodes within the core;

a shared cache for supplying instructions and operands to the plurality of cores;

a self-test unit, receiving serial outputs from the scan test chains in each core, the self-test unit including;

compare means for comparing a serial output from a first core to the serial outputs from other cores;

voting means, coupled to the compare means, for determining a correct serial output, the correct serial output having a value matching a value of a serial output on another core;

error means, coupled to the voting means, for signaling an error when a serial output does not match the correct serial output;

wherein an external tester does not compare the serial output to an expected value but the voting means determined the correct serial output as a matching value, and

wherein the shared cache occupies a larger area of the die than the area occupied by a processor core, each processor core further comprising a local cache, coupled to the shared cache, for storing instructions and operands for use by a local processor core.