Consistently specifying way destinations through prefetching hints

• US 5,732,242 A
• Filed: 03/24/1995
• Issued: 03/24/1998
• Est. Priority Date: 03/24/1995
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Mowry, Todd C.
• Primary Examiner(s): Kim, Matthew M.
• Application Number:
  US08/410,524
• Time in Patent Office: 1,096 Days
• Field of Search: 395/464, 395/375, 395/421.03, 395/414, 395/415, 395/463, 395/449, 395/403, 395/381-383, 395/584, 395/455, 395/471
• US Class Current: 711/136
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination. The portion of the hint field identifying a destination may be applied to consistently direct streamed and retained data to select portions of a cache. As a result, one type of data (e.g., retained) is lees likely to be replaced by another type of data (e.g., streamed) and vice versa.

Claims

1. In a processor with an n-way cache, a method for prefetching comprising the steps of:

issuing a prefetch instruction, wherein said prefetch instruction includes a hint field and address information;

addressing the cache using said address information contained in said prefetch instruction;

indicating a cache miss for desired data that is addressed by said prefetch instruction;

specifying a refill destination for said desired data with a first portion of said hint field, wherein said destination is a first way in said cache when said desired data is streamed data and a second way in said cache when said desired data is retained data, said first portion being operable in subsequent prefetch instructions to consistently specify such way destinations for subsequent streamed and retained data; and

refilling said cache with said desired data.

2. The method of claim 1 further comprising the step of enabling said specifying step using a second portion of said hint field.

3. The method of claim 2 wherein said refilling step refills said first way of said cache and further comprising a third portion of said hint field which indicates whether said desired data is expected to be modified.

4. The method of claim 1 further comprising the step of disabling said specifying step using a second portion of said hint field.

5. The method of claim 4 further comprising the step of refilling said cache based on a least-recently-used protocol.

6. The method of claim 1 wherein said desired data is not prevented from being rewritten in any subsequent refill operation on the basis of said data being identified as retained or streamed when said refill destination is selected.

7. A processor comprising:

a decoder for decoding a prefetch instruction, wherein said prefetch instruction includes a hint field and address information;

a first n-way set-associative cache, coupled to said decoder, containing a first-cache line that is addressed using said address information;

a first comparator, coupled to said first n-way set associative cache, for indicating a first-cache miss when said first-cache line is addressed and does not contain desired data; and

a first multiplexer, coupled to said first n-way set-associative cache, for choosing a first destination indicator used to direct refilling of said first-cache line with said desired data, said first destination indicator being chosen from a first portion of said hint field and a first LRU bit, said first portion specifying a first way for desired data identified as streamed data and a second way for desired data identified as retained data, and said first LRU bit specifying a destination way for desired data identified as neither streamed nor retained data, said first portion being operable in subsequent refill operations to consistently specify first and second way destinations for subsequent streamed and retained data, respectively.

8. The processor of claim 7 wherein said first portion of said hint field points to said first way of said first cache, wherein said first way contains no desired data identified as retained data.

9. The processor of claim 8 further comprising a means for disabling a refill operation of said cache line when said first way is unavailable.

10. The processor of claim 7 wherein said first portion of said hint field points to said second way of said first cache, wherein said second way contains no desired data identified as streamed data.

11. The processor of claim 7 further comprising:

a second n-way set-associative cache, coupled to said first cache, containing a second cache line that is addressed using said address information;

a second comparator, coupled to said second cache, for indicating a second-cache miss when said second cache line is addressed; and

a second multiplexer, coupled to said second cache, for choosing a second destination indicator used to direct refilling of said second cache line with said desired data, said second destination indicator being chosen from said first portion of said hint field and a second LRU bit, said first portion being operable to consistently specify said first way for desired data identified as streamed data and said second way for desired data identified as retained data, and said second LRU bit specifying a destination way for desired data identified as neither streamed nor retained data.

12. The processor of claim 11 further comprising a third multiplexer, coupled to said second cache, for choosing a third destination indicator used to direct prefetching of said desired data from said second cache line, said third destination indicator being chosen from said first portion of said hint field and a first MRU bit.

13. The processor of claim 7 wherein said hint field includes a second portion which controls said first multiplexer.

14. The processor of claim 13 wherein said hint field includes a third portion that specifies whether desired data is expected to be modified.

20. The method of claim 13 wherein said alternative indicator is an LRU bit specifying a destination way for desired data identified as neither streamed nor retained data.

15. A processor comprising:

a decoder for decoding a prefetch instruction, said prefetch instruction including a hint field and being used to refill desired data to a first n-way cache; and

a first multiplexer, coupled to said decoder, for choosing a first destination indicator used to direct refilling of said first cache with said desired data, said first destination indicator being chosen from a first portion of said hint field and an alternative indicator under control of a second portion of said hint field, said first portion specifying a first way for desired data identified as streamed data and a second way for desired data identified as retained data, said first portion being operable in subsequent refill operations to consistently specify first and second way destinations for subsequent streamed and retained data, respectively.

16. The processor of claim 15 wherein said first portion of said hint field points to said first way of said first cache, wherein said first way contains no desired data identified as retained data.

17. The processor of claim 15 wherein said first portion of said hint field points to said second way of said first cache, wherein said second way contains no desired data identified as streamed data.

18. The processor of claim 15 further comprising:

a second multiplexer, coupled to said decoder, for choosing a second destination indicator used to direct reading of said desired data from a second cache.

19. The processor of claim 15 wherein said alternative indicator is a randomly generated bit.