MOS transistor and fabrication process therefor

• US 5,734,185 A
• Filed: 08/08/1996
• Issued: 03/31/1998
• Est. Priority Date: 12/01/1995
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Azuma, Kenichi, Kawamura, Akio, Iguchi, Katsuji
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/694,067
• Time in Patent Office: 600 Days
• Field of Search: 257/336, 257/344, 257/389, 257/401, 257/406, 257/408, 257/506, 438/29, 438/42, 438/228
• US Class Current: 257/336
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.

Claims

1. An MOS transistor comprising:

a semiconductor substrate having a field region;

a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and

source/drain regions formed in the semiconductor substrate;

wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film;

the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions;

the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and

the channel region being substantially leveled with the source/drain regions.

2. An MOS transistor as set forth in claim 1,

wherein the upper insulating film is formed of a material which is able to be etched at a rate 5 to 30 times higher than a material for the lower insulating film.

3. An MOS transistor as set forth in claim 1,

wherein the upper insulating film is formed of a silicon oxide film, and the lower insulating film is formed of a double-layer film comprised of a silicon nitride film/a silicon oxide film.

4. An MOS transistor as set forth in claim 1,

wherein the sidewall insulating layer includes a silicon oxide film and a silicon nitride film covering the silicon oxide film.

5. An MOS transistor as set forth in claim 1,

wherein the upper insulating film is formed of a silicon oxide film, the lower insulating film is formed of a double-layer film comprised of a silicon nitride film/a silicon oxide film, and the sidewall insulating layer includes a silicon oxide film and a silicon nitride film covering the silicon oxide.

6. A process for fabricating an MOS transistor, comprising the steps of:

(i) forming a lower insulating film and an upper insulating film on the entire surface of a semiconductor substrate, and forming an opening extending to the lower insulating film in the upper insulating film on a channel region and a periphery portion of the channel region;

(ii) forming a sidewall insulating layer of a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating films on a side wall of the opening formed in the upper insulating film, and removing a portion of the lower insulating film which is present in the bottom of the opening and does not underlie the sidewall insulating layer to expose the semiconductor substrate;

(iii) forming a gate insulating film on the exposed semiconductor substrate;

(iv) forming a gate electrode on the gate insulating film so that at least a portion of the sidewall insulating layer is covered therewith; and

(v) removing a portion of the upper insulating film which overlies regions where source/drain regions are to be formed, to form a sidewall spacer contacting a side wall of the gate electrode.

7. A process as set forth in claim 6,

wherein the lower insulating film is formed of a first insulating film and a second insulating film made of a material permitting the second insulating film to be selectively etched with respect to the first insulating film, in the step (i).

8. A process as set forth in claim 6,

wherein the lower insulating film is formed of a silicon nitride film/a silicon oxide film, and the upper insulating film is formed of a silicon oxide film, in the step (i).

9. A process as set forth in claim 6,

wherein the sidewall insulating layer is formed of a silicon nitride film and a silicon oxide film in this order on the upper insulating film including the opening, in the step (ii).

10. A process as set forth in claim 6, further comprising the step of:

(vi) forming source/drain regions by first-ion-implanting at an angle of not less than θ

₁ (tan θ

₁ =SG/Sh, where SG is a distance between an end of the sidewall spacer and an end of the gate electrode, Sh is the height of the sidewall spacer) and then second-ion-implanting at an angle of not less than θ

₂ (tan θ

₂ =BS/Sh, where BS is a distance between an end of a bottom surface of the gate electrode facing the channel region and an end of a top surface of the gate electrode) with use of the gate electrode and the sidewall spacer as a mask.