Method for implementing tri-state nets in a logic emulation system

• US 5,734,581 A
• Filed: 12/19/1996
• Issued: 03/31/1998
• Est. Priority Date: 10/05/1988
• Status: Expired due to Term

• Current Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Butts, Michael R., Batcheller, Jon A.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/769,659
• Time in Patent Office: 467 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 395/500, 326/37, 326/39, 326/41, 326/47, 326/56
• US Class Current: 703/15
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERQGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Claims

1. In an electronic circuit system, a method of implementing a tri-state net having no connections outside the emulation system, the tri-state net being in a netlist defining a circuit design and having a plurality of tri-state drivers, the tri-state drivers each having an input, an enable and an output connected to the tri-state net, the method comprising the steps of:

substituting an AND gate having a first input and a second input for each of the plurality of tri-state drivers in the net, said first input of said AND gate being the input of the tri-state driver and said second input of said AND gate being the enable of the tri-state driver;

connecting outputs of each of said AND gates to an OR gate having an output; and

connecting said output of said OR gate to the tri-state net.

2. In an electronic circuit system, a method of implementing a tri-state net that is routed from a first circuit board to a second circuit board, the tri-state net being in a netlist defining an integrated circuit design and having a plurality of tri-state drivers, each of the tri-state drivers having an input, an enable and an output connected to the tri-state net, comprising the steps of:

substituting a first AND gate having a first input and a second input for each of the plurality of tri-state drivers in the tri-state net located on the first circuit board, said first input of said first AND gate being the input of the tri-state driver and said second input being the enable of the tri-state driver;

connecting an output of each of said first AND gates to a first OR gate having an output, said first OR gate being located in the first circuit board;

connecting said output of said first OR gate to an input of a second OR gate;

substituting a second AND gate having a first input and a second input for each of the plurality of tri-state drivers in the tri-state net located on the second circuit board, said first input of said second AND gate being the input of the tri-state driver and said second input being the enable of the tri-state driver;

connecting an output of each said second AND gate to a third OR gate having an output, said third OR gate being located on the second circuit board;

connecting said output of said third OR gate to an input of said second OR gate; and

connecting the output of said second OR gate to the tri-state net located in the first circuit board and the second circuit board.