Semiconductor memory device having cell array divided into a plurality of cell blocks

• US 5,734,619 A
• Filed: 09/15/1992
• Issued: 03/31/1998
• Est. Priority Date: 11/13/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Numata, Kenji, Fujii, Syuso
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/944,729
• Time in Patent Office: 2,023 Days
• Field of Search: 365/230.03, 365/203, 365/230.06
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

Claims

1. A Dynamic Random Access Memory, comprising:

a cell array divided into a plurality of cell blocks, each cell block including,

a plurality of memory cells arranged in a matrix form,

a plurality of word lines, arranged in a column direction, for selecting said memory cells in the column direction,

a plurality of bit lines, arranged to cross said word lines, for transferring data to/from said selected memory cell, and,

bit line sense amplifiers respectively connected to said bit lines;

cell block selection means for selecting one of said plurality of cell blocks on active cycle;

a plurality of data I/O lines to which said bit lines in a selected cell block selected by said cell block selection means are connected through respective column selection gates;

row decoder for selectively driving said word lines in each cell block;

a plurality of column selection signal lines arranged across said plurality of cell blocks, each column selection signal line commonly connected to associated column selection gates in a same column of said plurality of cell blocks;

column decoder for transferring column selection signals to said column selection signal lines; and

data buffer means, connected to said respective data I/O lines, for sensing data read out to said respective data I/O lines, said data buffer means including,

first precharge means, connected to said data I/O lines, for precharging said data I/O lines at the same first potential as a precharge potential of said bit lines,

second precharge means, connected to said data I/O lines, for precharging said data I/O lines at a second potential different from the precharge potential of said bit lines,

selective drive means for generating control signals to be supplied to said first and second precharge means, and selectively driving said first and second precharge means to sense the data read out to said data I/O lines on the basis of the control signals, such that said first precharge means precharges said data I/O lines connected to non-selected cell blocks of said cell blocks to the first potential on active cycle and on precharge cycle, and precharges a selected data I/O line connected to said selected cell block to the first potential on precharge cycle, and said second precharge means precharges said selected data I/O line connected to said selected cell block to the second potential on active cycle, and

I/O line sense amplifiers for sensing the data read out to said data I/O lines.

2. A semiconductor memory device according to claim 1, wherein said first precharge means precharges said data I/O lines connected to non-selected cell blocks of said cell blocks to (1/2)Vcc on active cycle and on precharge cycle, and precharges said data I/O lines connected to said selected cell block to (1/2)Vcc on precharge cycle.

3. A semiconductor memory device according to claim 2, wherein said first precharge means is arranged between a pair of said data I/O lines and is connected to a (1/2)Vcc terminal.

4. A semiconductor memory device according to claim 1, wherein said second precharge means precharges said data I/O lines connected to said selected cell block to Vcc on active cycle.

5. A semiconductor memory device according to claim 4, wherein second precharge means is arranged between a pair of said data I/O lines and is connected to a Vcc terminal.

6. A semiconductor memory device according to claim 1, wherein said precharge selective drive means is controlled by cell block selection signals for selecting said adjacent cell blocks, and generates the control signals.

7. A semiconductor memory device according to claim 1, wherein said data buffer means is shared by said adjacent cell blocks.

8. A semiconductor memory device according to claim 1, wherein at least some of said bit line sense amplifiers and said data I/O lines are shared by said adjacent cell blocks.

9. A semiconductor memory device according to claim 1, wherein each of said bit line sense amplifiers is constituted by a PMOS sense amplifier arranged in each of said cell blocks, and an NMOS sense amplifier arranged outside said cell block selection gates of said cell blocks and shared by said two adjacent cell blocks.

16. The Dynamic Random Access Memory according to claim 1, wherein the second potential is higher than the first potential.

10. A Dynamic Random Access Memory, comprising:

a cell array divided into a plurality of cell blocks, each cell block including,

a plurality of memory cells arranged in a matrix form,

a plurality of word lines, arranged in a column direction, for selecting said memory cells in the column direction,

a plurality of bit lines, arranged to cross said word lines, for transferring data to/from said selected memory cells, said bit lines being precharged to a first potential, and,

bit line sense amplifiers respectively connected to said bit lines;

cell block selection means for selecting one of said plurality of cell blocks on active cycle;

a plurality of data I/O lines to which said bit lines in a selected cell block selected by said cell block selection means are connected through respective column selection gates, a selected I/O line of said selected cell block having a second potential different from said first potential on an active cycle, and having said first potential on a precharge cycle, non-selected data I/O lines in non-selected cell blocks having the first potential on the active cycle and the precharge cycle;

row decoder for selectively driving said word lines in each cell block;

a plurality of column selection signal lines arranged across said plurality of cell blocks, each column selection signal line commonly coupled to associated column selection gates in a same column of said plurality of cell blocks;

column decoder for generating column selection signals to said column selection signal lines; and

selection gate control means, provided between said column selection signal lines and said column selection gates, for receiving the associated column selection signal and gating the column selection gate of the selected cell block on the active cycle on the basis of the associated column selection signal, thereby precharging said selected I/O line of said selected cell block to the second potential and maintaining said non-selected I/O lines of non-selected blocks to the first potential on the active cycle.

11. A semiconductor memory device according to claim 10, wherein said selection gate control means is arranged between said column selection signal lines and said column selection gates and is controlled by a pair of control signals from said cell block selection means for selecting said adjacent cell blocks.

12. A semiconductor memory device according to claim 11, wherein said selection gate control means is constituted by an NAND gate for receiving the respective cell block selection signals for said adjacent cell blocks, and an AND gate for receiving an output from said NAND gate and the column selection signals.

13. A semiconductor memory device according to claim 12, wherein said AND gate is constituted by an inverter, a transfer gate consisting of an n-channel MOS transistor and a p-channel MOS transistor, and an n-channel MOS transistor for short circuit.

14. A semiconductor memory device according to claim 10, wherein at least some of said bit line sense amplifiers and said data I/O lines are shared by said adjacent cell blocks.

15. A semiconductor memory device according to claim 10, wherein each of said bit line sense amplifiers is constituted by a PMOS sense amplifier arranged in each of said cell blocks, and an NMOS sense amplifier arranged outside said cell block selection gates of said cell blocks and shared by said adjacent cell blocks.

17. The Dynamic Random Access Memory according to claim 11, wherein the second potential is higher than the first potential.