Semiconductor device, semiconductor laser, and high electron mobility transistor

• US 5,734,670 A
• Filed: 04/15/1996
• Issued: 03/31/1998
• Est. Priority Date: 10/11/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Motoda, Takashi, Ono, Kenichi
• Primary Examiner(s): Healy, Brian
• Application Number:
  US08/632,149
• Time in Patent Office: 715 Days
• Field of Search: 372/43, 372/44, 372/45, 372/50, 257/15, 257/17, 257/18, 257/19, 257/185, 257/190, 257/191, 257/201
• US Class Current: 372/45.012
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01S 5/2231 with inner confining structure only between the active layer and the upper electrode
• CPC Class Codes: H01S 5/34 comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers H01S5/36 takes precedence
• CPC Class Codes: H01S 5/3403 having a strained layer structure in which the strain performs a special function, e.g. general strain effects, strain versus polarisation
• CPC Class Codes: H01S 5/34326 with a well layer based on InGa(Al)P, e.g. red laser

Abstract

A semiconductor device includes a semiconductor substrate having a surface; and a strained superlattice structure including first semiconductor layers having a first strain in a direction with respect to the semiconductor substrate and second semiconductor layers having a second strain in the same direction as and different in magnitude from the first strain, the first semiconductor layers and the second semiconductor layers being alternatingly laminated. The difference in strains between the first semiconductor layers and the second semiconductor layers is reduced, so that the crystalline quality of the strained superlattice structure is improved.

Claims

1. A semiconductor device including:

a semiconductor substrate having a surface; and

a strained superlattice structure comprising a plurality of first semiconductor layers having a first strain in a direction with respect to the semiconductor substrate and a plurality of second semiconductor layers having a second strain in the same direction as and different in magnitude from the first strain, the first semiconductor layers and the second semiconductor layers being alternatingly laminated and a difference between the second strain and the first strain gradually decreases in absolute value from a second semiconductor layer toward an adjacent first semiconductor layer.

2. A semiconductor device including:

a semiconductor substrate having a surface;

a strained superlattice structure comprising a plurality of first semiconductor layers having a first strain in a direction with respect to the semiconductor substrate and a plurality of second semiconductor layers having a second strain in the same direction as and different in magnitude from the first strain, the first semiconductor layers and the second semiconductor layers being alternatingly laminated; and

a third semiconductor layer in the vicinity of the strained superlattice structure, the third semiconductor layer being parallel to the surface of the substrate and having a third strain opposite in direction from the first strain.

3. A semiconductor laser comprising:

a semiconductor substrate of a first conductivity type and having opposed front and rear surfaces;

a first cladding layer of the first conductivity type disposed on the front surface of the semiconductor substrate, the first cladding layer having no strain with respect to the semiconductor substrate and having a band gap energy;

an active layer comprising a pair of separate confinement heterostructure layers disposed on the first cladding layer and a strained superlattice structure interposed between the separate confinement heterostructure layers, the separate confinement heterostructure layers comprising a material having a band gap energy smaller than the band gap energy of the first cladding layer, the strained superlattice structure comprising a plurality of well layers having a first strain in a direction with respect to the semiconductor substrate and a plurality of barrier layers interposed between the well layers and having a second strain in the same direction as and smaller than the first strain;

a second cladding layer of a second conductivity type, opposite the first conductivity type, disposed on the active layer and comprising the same material as the first cladding layer;

a contact layer of the second conductivity type disposed on the second cladding layer and having no strain with respect to the substrate;

a first electrode disposed on the substrate; and

a second electrode disposed on the contact layer.

4. The semiconductor laser of claim 3 including the separate confinement heterostructure layers having a third strain in the same direction as the first strain, the third strain gradually increasing toward the strained superlattice structure.

5. The semiconductor laser of claim 3 wherein the barrier layers have a third strain the same direction as the first strain and a difference between the third strain and the first strain gradually decreases in absolute value toward the well layer.

6. The semiconductor laser of claim 3 including a strain relaxing layer in the vicinity of the strained superlattice structure, the strain relaxing layer being parallel to the surface of the substrate, having a third strain opposite in direction from the first strain, and comprising a semiconductor material having a conductivity type and an energy band gap identical to those of a semiconductor layer contacting the strain relaxing layer.

7. The semiconductor laser of claim 3 wherein the semiconductor substrate comprises first conductivity type GaAs, the first cladding layer comprises first conductivity type (Al_x1 Ga_1-x1)_y1 In_1-y1 P (0<

x1<

1, 0<

y1<

1) having no strain with respect to the semiconductor substrate, the separate confinement heterostructure layers comprise (Al_x2 Ga_1-x2)_y2 In_1-y2 P (0<

x2≦

x1, y2=y1, the well layers comprise (Al_x3 Ga_1-x3)_y3 In_1-y3 P (0<

x3≦

x2, y2<

y3<

1), the barrier layers comprise (Al_x4 Ga_1-x4)_y4 In_1-y4 P (x4=x2, y2<

y4<

y3), the second cladding layer comprises second conductivity type (Al_x1 Ga_1-x1)_y1 In_1-y1 P, and the contact layer comprises second conductivity type GaAs.

8. A high electron mobility transistor comprising:

a semi-insulating substrate having a surface;

an undoped electron transit layer disposed on the surface of the semi-insulating substrate;

an undoped pseudo electron transit layer disposed on the electron transit layer and having a first strain in a direction with respect to the substrate;

an electron supply layer disposed on the pseudo electron transit layer and having a high concentration of a dopant impurity producing n type conductivity;

a gate electrode disposed on a portion of the electron supply layer, making a Schottky contact with the electron supply layer;

a source electrode and a drain electrode disposed on portions of the electron supply layer at opposite sides of and spaced apart from the gate electrode, making ohmic contacts with the electron supply layer; and

an n type crystalline defect preventing layer interposed between the pseudo electron transit layer and the electron supply layer and having a second strain in the same direction as and smaller than the first strain.

9. The high electron mobility transistor of claim 8 wherein the substrate comprises semi-insulating GaAs, the electron transit layer comprises undoped GaAs, the pseudo electron transit layer comprises undoped InGaAs, the electron supply layer comprises AlGaAs having a high concentration of a dopant impurity producing n type conductivity, and the crystalline defect preventing layer is selected from the group consisting of n type GaAsSb including a very small amount of antimony and n type InGaAs in which the In composition is controlled to make the second strain smaller than the first strain.

11. The high electron mobility transistor of claim 8 wherein the substrate comprises semi-insulating GaAs, the electron transit layer comprises undoped GaAs, the pseudo electron transit layer comprises undoped InGaAs, the electron supply layer comprises AlGaAs having a high concentration of an n type producing dopant impurity, and the crystalline defect preventing layer is selected from the group consisting of undoped GaAsSb including a very small amount of antimony and undoped InGaAs in which the In composition is controlled to make the second strain smaller than the first strain.

10. A high electron mobility transistor comprising:

a semi-insulating substrate having a surface;

a undoped electron transit layer disposed on the surface of the semi-insulating substrate;

an undoped pseudo electron transit layer disposed on the electron transit layer and having a first strain in a direction with respect to the substrate;

an electron supply layer disposed on the pseudo electron transit layer and having a high concentration of a dopant impurity producing n type conductivity;

a gate electrode disposed on a portion of the electron supply layer, making a Schotty contact with the electron layer;

a source electrode and a drain electrode disposed on portions of the electron supply layer at opposite sides of and spaced apart from the gate electrode, making ohmic contacts with the electron supply layer; and

an undoped crystalline defect preventing layer interposed between the pseudo electron transit layer and the electron transit layer and having a second strain in the same direction as and smaller than the first strain.