Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing method

• US 5,734,808 A
• Filed: 05/24/1995
• Issued: 03/31/1998
• Est. Priority Date: 09/28/1993
• Status: Expired due to Term

• Current Assignee: Namco Bandai Games Inc.
• Original Assignee: Namco Limited (BANDAI NAMCO Holdings Inc.)
• Inventors: Takeda, Masaki
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/436,425
• Time in Patent Office: 1,042 Days
• Field of Search: 395/134, 395/513
• US Class Current: 345/419
• CPC Class Codes: G06T 15/30 Clipping

Abstract

An objective of this invention is to provide a pipeline processing device that enables the implementation of optimized pipeline processing and moreover has a simple configuration and control method, and a clipping processing device that uses this pipeline processing device. Data is sequentially transferred to pipeline register sections (500 to 506), but only when there is processing data in each previous stage, and given data processing is performed in data processing sections (520 to 524). After the end of input of processing data in which a plurality of data items is formed into one string D 0:3!, this data is automatically extracted from the pipeline register sections (500 to 506). These transfer and automatic extraction operations in the pipeline control sections (530 to 536) are controlled by an LD signal. This LD signal is formed by ENIN and FLASHIN signals.

Claims

1. A pipeline processing device for transferring processing data by pipeline processing, comprising:

a plurality of serially connected pipeline registers for sequentially transfer which processing data in which a plurality of data items are formed into one string; and

pipeline control means, to which a pipeline drive signal and a flash signal are input, for controlling data transfer in said plurality of pipeline registers on the basis of said pipeline drive signal and said flash signal, said pipeline control means comprising;

means for permitting data transfer to one pipeline register among said plurality of serially connected pipeline registers from a previous serially connected pipeline register only when processing data is present in the serially connected pipeline register and said pipeline drive signal has been enabled; and

means for automatically extracting from said plurality of serially connected pipeline registers one string of processing data that has already been input when said flash signal has been enabled, independently of said pipeline drive signal being enabled or disabled.

2. A pipeline processing device for transferring processing data by pipeline processing, comprising:

a plurality of serially connected pipeline registers using a transfer clock to sequentially transfer processing data in which a plurality of data items are formed into one string; and

a plurality of pipeline control means, each connected to one of said plurality of serially connected pipeline registers, for generating and outputting a signal that enables data transfer to a pipeline register from a previous serially connected pipeline register using said transfer clock;

wherein each of said pipeline control means comprises;

pipeline drive permitting means for;

generating a signal that transfers data to that pipeline register connected to the pipeline control means from a previous serially connected pipeline register connected to a pipeline control means when one of an input pipeline drive signal and an input flash signal input to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register is enabled, and also holding said input pipeline drive signal in a first memory means of the pipeline control means connected to said pipeline register, and

enabling an output pipeline drive signal to be output from the pipeline control means connected to said pipeline register to a pipeline control means connected to a subsequent serially connected pipeline register when both

     1) an input pipeline drive signal held in said first memory means, and

     2) said input pipeline drive signal input to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register, are enabled; and

flash permitting means for;

holding the input flash signal input to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register in a second memory means of the pipeline control means connected to said pipeline register, and

enabling an output flash signal output from the pipeline control means connected to said pipeline register to the pipeline control means connected to the subsequent serially connected pipeline register when either an input flash signal held in said second memory means one transfer clock period previously or said input flash signal inputted to the pipeline control means connected to said pipeline register from the pipeline control means connected to the previous serially connected pipeline register is enabled.

3. The pipeline processing device as defined in claim 2, wherein said pipeline drive permitting means comprises means for clearing data held in said first memory means and said data clearing means initializes said pipeline processing device by clearing said data held in said first memory means.

4. A clipping processing device for performing clipping processing using a plurality of clipping surfaces with respect to a three-dimensional object represented by a plurality of polygons, comprising:

inside/outside decision means for determining whether a polygon is divided by a clipping surface on the basis of input polygon image data;

interior-division-point calculation means for using said input polygon image data to calculate interior division points for said polygon when said inside/outside decision means determines said polygon is divided; and

output control means for generating a pipeline drive signal and a flash signal and outputting said pipeline drive and flash signals to said interior-division-point calculation means;

wherein said interior-division-point calculation means comprises;

a plurality of serially connected pipeline registers for sequentially transferring polygon image data in which a plurality of data items are formed into one string; and

pipeline control means, to which said pipeline drive signal and said flash signal are input from said output control means, for controlling data transfer in said pipeline registers on the basis of said pipeline drive signal and said flash signal, said pipeline control means comprising;

means for permitting data transfer to one pipeline register among said plurality of pipeline registers from a previous serially connected pipeline register only when polygon image data is present in the previous serially connected pipeline register and said pipeline drive signal has been enabled; and

means for automatically extracting from said plurality of pipeline registers one string of polygon image data that has already been input when said flash signal has been enabled, independently of said pipeline drive signal being enabled or disabled.

5. The clipping processing device as defined in claim 4, wherein:

said interior-division-point calculation means comprises a division means for performing a division that divides a distance between vertex coordinates of a polygon; and

said output control means comprises means for detecting completion of a division performed by said division means and means for enabling said pipeline drive signal when division completion has been detected by said detection means.

6. The clipping processing device as defined in claim 4, further comprising:

means for re-inputting polygon image data for which clipping processing using one clipping surface has ended to said inside/outside decision means and said interior-division-point calculation means, and thus subjecting said polygon image data to clipping processing using another clipping surface.

7. A three-dimensional simulator device comprising a clipping processing device as defined in claim 4, further comprising:

image synthesis means for synthesizing a field-of-view image as seen from an observer within a virtual three-dimensional space, using a polygon that has been subjected to clipping processing by said clipping processing device.

8. A pipeline processing method comprising:

using a pipeline drive signal and a flash signal to control data transfer between a plurality of serially connected pipeline registers, wherein a plurality of data items are formed into one string;

which is input into the plurality of serially connected pipeline registers;

permitting data transfer to a pipeline register from a previous serially connected pipeline register only when processing data exists in the previous serially connected pipeline register and said pipeline drive signal has been enabled; and

automatically extracting one string of processing data that has already been input when said flash signal is enabled, independently of said pipeline drive signal being enabled or disabled.