System and method for generating supplemental ready signals to eliminate wasted cycles between operations

• US 5,734,856 A
• Filed: 07/01/1996
• Issued: 03/31/1998
• Est. Priority Date: 04/05/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/673,465
• Time in Patent Office: 638 Days
• Field of Search: 395/376, 395/395
• US Class Current: 712/219
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A data processing system comprising a controller, a functional unit coupled to the controller, to perform a first operation having an operational latency, and a supplemental ready signal generator coupled to the controller. The functional unit requires an initial lead time period before beginning a second operation. After the supplemental ready signal generator receives a first load signal it forwards a supplemental ready signal to the controller. The timing of the supplemental ready signal is a function of the operational latency. The supplemental ready signal indicates to the controller when the functional unit will output results corresponding to the first operation. The controller can then send a second load signal to the functional unit early enough to accommodate the initial lead time period, thereby permitting the functional unit to perform the second operation after the first operation completes without incurring wait cycles between the first and second operations.

Claims

1. A data processing system comprising:

a controller to generate first and second load signals;

a functional unit coupled to said controller,

wherein upon receipt of said first and second load signals said functional unit begins first and second operations, respectively, said first operation having an operational latency; and

a supplemental ready signal generator coupled to said controller, to receive said first load signal and forward a supplemental ready signal to said controller,

wherein timing of said supplemental ready signal is a function of said operational latency of said first operation and an initial lead time period required to begin said second operation, and

wherein said supplemental ready signal is received by said controller so that said controller can send said second load signal to said functional unit thereby enabling said functional unit to perform said second operation after said first operation completes without incurring wait cycles between said first and second operations.

2. The data processing system according to claim 1, wherein said supplemental ready signal generator comprises means for waiting one or more cycles after receiving said first load signal and then sending said second load signal to said functional unit.

3. The data processing system according to claim 2, wherein said means for waiting determines how long to wait based on said first operation.

4. The data processing system according to claim 2, wherein said means for waiting comprises a decoder to determine how many cycles to wait based on said first operation.

5. The data processing system according to claim 2, wherein said means for waiting comprises a decoder to decode opcode information to determine how many cycles to wait after receiving said first load signal.

6. The data processing system according to claim 3, wherein said means for waiting comprises a counter.

7. The data processing system according to claim 4, wherein said means for waiting includes a counter coupled to said decoder.

8. The data processing system according to claim 6, wherein said counter is a binary counter.

9. The data processing system according to claim 6, wherein said counter is a polynomial counter.

10. The data processing system according to claim 1, wherein said functional unit is located within a pipeline.

11. The data processing system according to claim 1, wherein said controller comprises a state machine.

12. In a data processing system comprising a functional unit, a controller coupled to said functional unit and a supplemental ready signal generator coupled to said controller, a method comprising the steps of:

forwarding a first load signal to said functional unit and said supplemental ready signal generator;

performing a first operation having an operational latency;

forwarding a supplemental ready signal to said controller, wherein timing of said supplemental ready signal is a function of said operational latency and an initial lead time period required to begin a second operation;

sending a second load signal to said functional unit; and

performing said second operation after said first operation completes without incurring wait cycles between said first and second operations.

13. The method according to claim 12, further comprising the steps of:

waiting one or more cycles after said first load signal; and

sending said second load signal to said functional unit.

14. The method according to claim 12, further comprising the step of:

determining how long to wait based on said first operation.

15. The method according to claim 12, further comprising the step of:

decoding the first operation to determine how many cycles to wait before forwarding said supplemental ready signal and counting said determined number of cycles.

16. The method according to claim 15, wherein said counting is binary counting.

17. The method according to claim 15, wherein said counting is polynomial counting.

18. A data processing system comprising:

a controller to generate first and second load signals;

first and second functional units coupled to said controller,

wherein upon receipt of said first and second load signals said first and second functional units begin first and second operations, respectively, said first operation having an operational latency; and

a supplemental ready signal generator coupled to said controller, to receive said first load signal and forward a supplemental ready signal to said controller,

wherein timing of said supplemental ready signal is a function of said operational latency of said first operation and an initial lead time period required to begin said second operation, and

wherein said supplemental ready signal is received by said controller so that said controller can send said second load signal to said second functional unit;

thereby enabling said second functional unit to perform said second operation after said first operation completes without incurring wait cycles between said first and second operations.

19. The data processing system according to claim 18, wherein said supplemental ready signal generator comprises means for waiting one or more cycles after receiving said first load signal and then-sending said second load signal to said second functional unit.

20. The data processing system according to claim 19, wherein said means for waiting determines how long to wait based on said first operation.

21. The data processing system according to claim 19, wherein said means for waiting comprises a decoder to determine how many cycles to wait based on said first operation.

22. The data processing system according to claim 19, wherein said means for waiting comprises a decoder to decode opcode information to determine how many cycles to wait after receiving said first load signal.

23. The data processing system according to claim 20, wherein said means for waiting comprises a counter.

24. The data processing system according to claim 21, wherein said means for waiting includes a counter coupled to said decoder.

25. The data processing system according to claim 23, wherein said counter is a binary counter.

26. The data processing system according to claim 23, wherein said counter is a polynomial counter.

27. The data processing system according to claim 18, wherein said functional unit is located within a pipeline.

28. The data processing system according to claim 18, wherein said controller comprises a state machine.

29. In a data processing system comprising first and second functional units, a controller coupled to each functional unit, and a supplemental ready signal generator coupled to said controller, a method comprising the steps of:

forwarding a first load signal to said first functional unit and said supplemental ready signal generator;

performing a first operation having an operational latency;

forwarding a supplemental ready signal to said controller, wherein timing of said supplemental ready signal is a function of said operational latency and an initial lead time period required to begin a second operation;

sending a second load signal to said second functional unit; and

performing said second operation after said first operation completes without incurring wait cycles between said first and second operations.

30. The method according to claim 29, further comprising the steps of:

waiting one or more cycles after said first load signal; and

sending said second load signal to said second functional unit.

31. The method according to claim 29, further comprising the step of determining how long to wait based on said first operation.

32. The method according to claim 29, further comprising the step of decoding the first operation to determine how many cycles to wait before forwarding said supplemental ready signal and counting said determined number of cycles.

33. The method according to claim 32, wherein said counting is binary counting.

34. The method according to claim 32, wherein said counting is polynomial counting.