Microcomputer in which a CPU is operated on the basis of a clock signal input into one of two clock terminals

• US 5,734,878 A
• Filed: 10/20/1995
• Issued: 03/31/1998
• Est. Priority Date: 06/28/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hongo, Katsunobu
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US08/546,126
• Time in Patent Office: 893 Days
• Field of Search: 395/559, 395/560, 395/750
• US Class Current: 713/600
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

A microcomputer constituted so that an oscillation state selection signal indicative of whether a clock inputted to a first clock terminal is a clock generated at a clock generating circuit is given to a first gate circuit interposed between a first clock terminal and a second clock terminal, and a first gate circuit is placed in the transmissible state when an oscillation state selection signal is on a first state while a first gate circuit is placed in a state not to be able to transmit a signal when the oscillation state selection signal is on a second state.

Claims

1. A microcomputer in which a CPU is operated on the basis of a clock signal inputted to a first clock terminal, comprising:

said first clock terminal and a second clock terminal to which a clock generating circuit is to be connected;

a first gate circuit provided between said first and second clock terminals so as to allow the clock generating circuit to be oscillated when in a transmissible state to transmit a signal; and

a second gate circuit for providing to the first gate circuit a first signal which is a logical OR of a stop signal for suspending the oscillation of the clock signal and an oscillation state selection signal indicative of whether the clock signal inputted to the first clock terminal is a clock signal generated by the clock generating circuit,

wherein said first gate circuit is placed in the transmissible state when the first signal is on a first level, and in a state in which it is not able to transmit a signal when the first signal is on a second level.

2. A microcomputer according to claim 1, further comprising a third gate circuit whose output terminal is connected to the second clock terminal, said third gate circuit being able to be placed in a floating state,

wherein said first gate circuit can be placed in the floating state,

said second gate circuit provides said first signal to said first gate circuit and said third gate circuit,

when said first signal is on the first level, said first gate circuit is in the transmissible state and said third gate circuit is placed in the floating state,

when said first signal is on the second level, said first gate circuit is in the floating state and said third gate circuit is in the transmissible state.

3. A microcomputer according to claim 2, further comprising:

a fourth gate circuit which is connected in parallel to said first gate circuit, and is able to be placed in the floating state; and

a fifth gate circuit for providing to the fourth gate circuit a second signal which is a logical OR of the first signal and a driving efficiency selection signal for selecting a driving efficiency for the clock generating circuit,

wherein said fourth gate circuit is placed in the transmissible state when the second signal is on the first level, and in the floating state when the signal is on the second level.

4. A microcomputer according to claim 3, further comprising:

counting means for counting clocks inputted to the first clock terminal since the supply of clocks is started or resumed; and

a sixth gate circuit for supplying a clock to the CPU;

wherein said sixth gate circuit is kept in the non-transmissible state until said counting means counts a predetermined number when the oscillation state selection signal is on the first level, and placed in the transmissible state when the oscillation state selection signal is on the second level.

5. A microcomputer according to claim 4, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal; and

an AND gate circuit for providing to the seventh gate circuit an AND signal of a wait signal for suspending the operation of the CPU, and a wait state selection signal for selecting the suspension or non-suspension of the operation of peripheral circuits;

wherein said seventh gate circuit is placed in the transmissible state when the wait state selection signal or the wait signal is on the first level, and in the non-transmissible state when the wait state selection signal and the wait signal are both on the second level.

6. A microcomputer according to claim 5 further comprising an input terminal for inputting an oscillation state selection signal, or an input terminal for inputting a wait state selection signal.

7. A microcomputer according to claim 4 further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal;

wherein said seventh gate circuit is placed in the transmissible state when a wait signal for suspending the operation of the CPU is on the first level, and in the non-transmissible state when the wait signal is on the second level.

8. A microcomputer according to claim 3, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal; and

an AND gate circuit for providing to the seventh gate circuit an AND signal of a wait signal for suspending the operation of the CPU, and a wait state selection signal for selecting the suspension or non-suspension of the operation of peripheral circuits;

wherein said seventh gate circuit is placed in the transmissible state when the wait state selection signal or the wait signal is on the first level, and in the non-transmissible state when the wait state selection signal and the wait signal are both on the second level.

9. A microcomputer according to claim 8 further comprising an input terminal for inputting an oscillation state selection signal, or an input terminal for inputting a wait state selection signal.

10. A microcomputer according to claim 3, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal;

wherein said seventh gate circuit is placed in the transmissible state when a wait signal for suspending the operation of the CPU is on the first level, and in the non-transmissible state when the wait signal is on the second level.

11. A microcomputer according to claim 2, further comprising:

counting means for counting clocks inputted to the first clock terminal since the supply of clocks is started or resumed; and

a sixth gate circuit for supplying a clock to the CPU;

wherein said sixth gate circuit is kept in the non-transmissible state until said counting means counts a predetermined number when the oscillation state selection signal is on the first level, and placed in the transmissible state when the oscillation state selection signal is on the second level.

12. A microcomputer according to claim 11, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal; and

an AND gate circuit for providing to the seventh gate circuit an AND signal of a wait signal for suspending the operation of the CPU, and a wait state selection signal for selecting the suspension or non-suspension of the operation of peripheral circuits;

wherein said seventh gate circuit is placed in the transmissible state when the wait state selection signal or the wait signal is on the first level, and in the non-transmissible state when the wait state selection signal and the wait signal are both on the second level.

13. A microcomputer according to claim 12 further comprising an input terminal for inputting an oscillation state selection signal, or an input terminal for inputting a wait state selection signal.

14. A microcomputer according to claim 11, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal;

wherein said seventh gate circuit is placed in the transmissible state when a wait signal for suspending the operation of the CPU is on the first level, and in the non-transmissible state when the wait signal is on the second level.

15. A microcomputer according to claim 2, further comprising:

a seventh gate circuit for supplying to the CPU a clock supplied to the first clock terminal or the second clock terminal; and

an AND gate circuit for providing to the seventh gate circuit an AND signal of a wait signal for suspending the operation of the CPU, and a wait state selection signal for selecting the suspension or non-suspension of the operation of peripheral circuits;

wherein said seventh gate circuit is placed in the transmissible state when the wait state selection signal or the wait signal is on the first level, and in the non-transmissible state when the wait state selection signal and the wait signal are both on the second level.

16. A microcomputer according to claim 15 further comprising an input terminal for inputting an oscillation state selection signal, or an input terminal for inputting a wait state selection signal.

17. A microcomputer according to claim 2, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal;

wherein said seventh gate circuit is placed in the transmissible state when a wait signal for suspending the operation of the CPU is on the first level, and in the non-transmissible state when the wait signal is on the second level.

18. A microcomputer according to claim 1, further comprising:

counting means for counting clocks inputted to the first clock terminal since the supply of clocks is started or resumed; and

a sixth gate circuit for supplying a clock to the CPU,

wherein said sixth gate circuit is kept in the non-transmissible state until said counting means counts a predetermined number when the oscillation state selection signal is on the first level, and placed in the transmissible state when the oscillation state selection signal is on the second level.

19. A microcomputer according to claim 18, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal; and

an AND gate circuit for providing to the seventh gate circuit an AND signal of a wait signal for suspending the operation of the CPU, and a wait state selection signal for selecting the suspension or non-suspension of the operation of peripheral circuits;

wherein said seventh gate circuit is placed in the transmissible state when the wait state selection signal or the wait signal is on the first level, and in the non-transmissible state when the wait state selection signal and the wait signal are both on the second level.

20. A microcomputer according to claim 19 further comprising an input terminal for inputting an oscillation state selection signal, or an input terminal for inputting a wait state selection signal.

21. A microcomputer according to claim 18, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal;

wherein said seventh gate circuit is placed in the transmissible state when a wait signal for suspending the operation of the CPU is on the first level, and in the non-transmissible state when the wait signal is on the second level.

22. A microcomputer according to claim 1, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal; and

an AND gate circuit for providing to the seventh gate circuit an AND signal of a wait signal for suspending the operation of the CPU, and a wait state selection signal for selecting the suspension or non-suspension of the operation of peripheral circuits;

wherein said seventh gate circuit is placed in the transmissible state when the wait state selection signal or the wait signal is on the first level, and in the non-transmissible state when the wait state selection signal and the wait signal are both on the second level.

23. A microcomputer according to claim 22 further comprising an input terminal for inputting an oscillation state selection signal, or an input terminal for inputting a wait state selection signal.

24. A microcomputer according to claim 1, further comprising:

a seventh gate circuit for supplying to the CPU a clock given to the first clock terminal or the second clock terminal;

wherein said seventh gate circuit is placed in the transmissible state when a wait signal for suspending the operation of the CPU is on the first level, and in the non-transmissible state when the wait signal is on the second level.