Saturation instruction in a data processor

• US 5,734,879 A
• Filed: 03/22/1995
• Issued: 03/31/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/409,761
• Time in Patent Office: 1,105 Days
• Field of Search: 395/375, 395/562, 395/563, 364/745, 364/748
• US Class Current: 712/221
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A method for executing a data processing instruction comprising the steps of:

receiving a data processing instruction;

decoding the data processing instruction to provide a plurality of control signals;

providing one of a scalar data value and a portion of a vector data value as an operand of the data processing instruction;

accessing an overflow value from a first storage location, the overflow value being asserted when a result is not one of a range of data values, the overflow value being negated when the result is one of the range of data values; and

modifying the result to be equal to a predetermined value when the overflow value is asserted.

2. The method of claim 1 further comprising the step of:

executing a data processing operation in response to the plurality of control signals, the data processing operation generating a result.

3. The method of claim 1 further comprising the steps of:

accessing an overflow direction value from a second storage location, wherein;

when the overflow direction value is asserted, the result is greater than a maximum value, and

when the overflow direction value is negated, the result is less than a minimum value.

4. The method of claim 3 wherein the predetermined value is a most positive number when the overflow value is asserted and the overflow direction value is asserted.

5. The method of claim 3 wherein the predetermined value is one of a most negative number and zero when the overflow value is asserted and the overflow direction value is negated.

6. The method of claim 3 wherein the result is a two'"'"'s complement signed data value.

7. The method of claim 6 wherein the predetermined value is equal to a hexadecimal value of $7F when the overflow value is asserted and the overflow direction value is asserted.

8. The method of claim 6 wherein the predetermined value is equal to a hexadecimal value of $80 when the overflow value is asserted and the overflow direction value is negated.

9. The method of claim 3 wherein the result is an unsigned data value.

10. The method of claim 9 wherein the predetermined value is equal to a hexadecimal value of $FF when the overflow value is asserted and the overflow direction value is asserted.

11. The method of claim 9 wherein the predetermined value is equal to a hexadecimal value of $00 when the overflow value is asserted and the overflow direction value is negated.

12. The method of claim 1 wherein the first storage location is a portion of a user programmable register.

13. The method of claim 12, wherein:

when the operand is the scalar data value, the data processing instruction has a mnemonic form of "sat"; and

when the operand is the portion of the vector data value, the data processing instruction has a mnemonic form of "vsat".

14. A data processor, comprising:

circuitry for receiving a first vector instruction and a second vector instruction;

a vector engine, comprising a plurality of processing elements for executing the first and second vector instructions, each one of the plurality of processing elements comprising;

control circuitry for controlling operation of that one of the plurality of processing elements;

circuitry for producing a result value during execution of the first instruction;

circuitry for producing an overflow indicator during execution of the first instruction; and

circuitry for selectively modifying the result value during execution of the second instruction so that the result value is equal to a predetermined value when the overflow indicator indicates that overflow has occurred.

15. A data processor as in claim 14, wherein the overflow indicator is stored in a portion of a user programmable register.

16. A method for executing a first data processing instruction and a second data processing instruction, the method comprising the steps of:

receiving a first data processing instruction;

providing one of a scalar data value and a portion of a vector data value as an operand of the first data processing instruction;

decoding the first data processing instruction to provide a first plurality of control signals;

during execution of the first data processing instruction, producing a result value and an overflow indicator;

during execution of the first data processing instruction, storing the result value in a first storage circuit and storing the overflow indicator in a second storage circuit;

receiving a second data processing instruction;

decoding the second data processing instruction to provide a second plurality of control signals; and

during execution of the second data processing instruction, modifying the result value to be equal to a predetermined value when the overflow indicator stored in the second storage circuit indicates that an overflow occurred during execution of the first instruction.

17. A data processor as in claim 16, wherein the second storage circuit is a portion of a user programmable register.