Low power consumption semiconductor integrated circuit device and microprocessor

• US 5,734,913 A
• Filed: 06/05/1995
• Issued: 03/31/1998
• Est. Priority Date: 12/15/1989
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tanaka, Shigeya, Iwamura, Masahiro, Nakano, Tetsuo, Maejima, Hideo
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/462,662
• Time in Patent Office: 1,030 Days
• Field of Search: 395/750, 395/775, 395/800, 395/375, 395/389, 395/388, 395/560, 395/557, 395/556, 395/555, 395/494, 395/496, 365/227
• US Class Current: 713/322
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Claims

1. A method for controlling power consumption in a semiconductor circuit device having at least one functional circuit block, wherein a subject instruction is executed by a selected functional circuit block of said at least one functional circuit block, said method comprising the steps of:

detecting whether said at least one functional circuit block is required for execution of said subject instruction by a result of decoding said subject instruction;

activating said at least one functional circuit block responsive to said subject instruction, from low power mode to normal operation mode when said at least one functional block is required for execution; and

deactivating said at least one functional circuit block responsive to said subject instruction, from said normal operation mode to said low power mode after execution of said subject instruction.

2. A method as defined claim 1, wherein said activating step includes the step of supplying a clock to said at least one functional block, and said deactivating step includes the step of stopping supply of a clock to said at least one functional block.

3. A method as defined in claim 1, wherein said activating step includes the step of increasing a circuit current of said at least one functional circuit block to a predetermined level in a predetermined time and said deactivating step includes the step of reducing said circuit current to a low power mode current in a predetermined time.

4. A semiconductor integrated circuit device comprising:

a functional circuit block having a power supply line inductance L, an allowable power supply noise V_n and a circuit current changing amplitude Δ

I; and

means for generating an operation previous notice signal to activate said functional circuit block a time T prior to a start of operation,

said T, L, V_n and Δ

I meeting a relation of ##EQU4##

5. A method for controlling power consumption of a functional circuit block comprising the steps of:

detecting whether said functional circuit block is required for execution of a subject instruction by a result of decoding said subject instruction, and if required, generating a previous notice signal responsive to said subject instruction, predicting a start of operation of said functional circuit block prior to the start of operation;

increasing a circuit current of said functional circuit block to a predetermined operation power level responsive to said subject instruction, in a predetermined time as measured starting from a time of reception of said previous notice signal to shift from a low power consumption mode to an operation mode;

executing an operation of said functional circuit block in said operation mode; and

reducing the circuit current to a predetermined level responsive to said subject instruction, in a predetermined time as measured after termination of execution of the operation of said functional circuit block to shift to the low power consumption mode.

6. A memory comprising:

a memory array;

an address decoder for selecting the memory array in response to an address signal to select the memory array;

a sense amplifier for amplifying a signal read from said memory array to a predetermined signal level; and

a current control signal generator for generating a current control signal to increase a circuit current of said memory array, an address decoder or said sense amplifier to a predetermined level in a predetermined time in response to an access previous notice signal for said memory array.

7. A memory according to claim 6 wherein said current control signal generator includes means for generating a control signal to reduce the circuit current of said memory array, said address decoder or said sense amplifier to a predetermined level in a predetermined time after the termination of the operation of said memory array, said address decoder or said sense amplifier.

8. A microprocessor for parallely fetching and decoding n (where n>

2) instructions and for parallely executing said n instructions by n arithmetic and logic units, comprising;

clock drivers for respectively supplying clocks to said n arithmetic and logic units;

a detector for detecting whether said n arithmetic and logic units are required for execution of said n instructions by a result of decoding said n instructions of said n arithmetic and logic units;

wherein said clock drivers start supplying clocks to said n arithmetic and logic units when said n arithmetic and logic units are required for use.

9. A microprocessor as defined in claim 8, wherein said clock drivers stop supplying clocks to said n arithmetic and logic units when said n arithmetic and logic units are not required for use.

10. A microprocessor comprising:

a program counter for indicating instructions to be read out from a memory;

a plurality of instruction registers for respectively storing instructions therein as indicated by said program counter;

a plurality of arithmetic and logic units for carrying out a parallel processing in accordance with instructions read from said instruction registers;

a detector for detecting a conflict between instructions in the parallel processing of instructions,

a clock driver circuit for respectively supplying clocks to said plurality of arithmetic and logic units,

wherein, when a conflict is detected by said detector, said clock driver circuit starts supplying said clock to at least one arithmetic and logic unit corresponding to at least one instruction to be executed prior to execution of said conflicted instructions.

11. A microprocessor comprising:

at least one functional circuit block, wherein an instruction is executed by a selected functional circuit block of said at least one functional circuit block;

a decoder for decoding a subject instruction and for detecting whether said at least one functional circuit block is required for execution of said subject instruction by a result of decoding said subject instruction;

an activating circuit for activating said at least one functional circuit block responsive to said subject instruction, from a low power mode to a normal operation mode when said at least one functional circuit block is required for execution, and deactivating said at least one functional circuit block responsive to said subject instruction, from said normal operation mode to said low power mode after execution of said subject instruction.

12. A microprocessor as defined in claim 11, wherein said activating circuit includes a clock driver circuit for supplying a clock to said at least one functional circuit block, wherein said clock driver circuit starts supplying said clock to said at least one functional circuit block when said at least one functional circuit block is required for execution.

13. A microprocessor as defined in claim 11, wherein said activating circuit includes a clock driver circuit for supplying a clock to said at least one function circuit block, wherein said clock driver circuit starts supplying said clock to said at least one functional circuit block when said at least one functional circuit block is required for execution, and wherein said clock driver circuit stops supplying said clock to said at least one functional circuit block when said at least one functional circuit block has carried out execution of said subject instruction.

14. A system having a microprocessor and a memory coupled to said microprocessor through a memory interface of said microprocessor,

wherein said microprocessor comprises;

at least one functional circuit block, wherein an instruction is executed by a selected functional circuit block of said at least one functional circuit block;

a decoder for decoding a subject instruction and for detecting whether said at least one functional circuit block is required for execution of said subject instruction by a result of decoding said subject instruction;

an activating circuit for activating said at least one functional circuit block responsive to said subject instruction, from a low power mode to a normal operation mode when said at least one functional circuit block is required for execution, and deactivating said at least one functional circuit block responsive to said subject instruction, from said normal operation mode to said low power mode after execution of said subject instruction.

15. A system as defined in claim 14, wherein said activating circuit includes a clock driver circuit for supplying a clock to said at least one functional circuit block, wherein said clock driver circuit starts supplying said clock to said at least one functional circuit block when said at least one functional circuit block is required for execution.

16. A microprocessor as defined in claim 14, wherein said activating circuit includes a clock driver circuit for supplying a clock to said at least one functional circuit block, wherein said clock driver circuit starts supplying said clock to said at least one functional circuit block when said at least one functional circuit block is required for execution, and wherein said clock driver circuit stops supplying said clock to said at least one functional circuit block when said at least one functional circuit block has carried out execution of said subject instruction.

17. A method for controlling power consumption in a semiconductor circuit device having at least one functional circuit block, wherein an instruction is executed by a selected functional circuit block of said at least one functional circuit block, said method comprising the steps of:

detecting whether said at least one functional circuit block is required for execution of an instruction by a result of decoding said instruction;

activating said at least one functional circuit block before execution of said instruction, from low power mode to normal operation mode when said at least one functional block is required for execution; and

deactivating said at least one functional circuit block responsive to completion of execution of said instruction, from said normal operation mode to said low power mode after execution of said instruction.

18. A method for controlling power consumption of a functional circuit block comprising the steps of:

detecting whether said functional circuit block is required for execution of an instruction by a result of decoding said instruction, and if required, generating a previous notice signal responsive to said instruction, predicting a start of operation of said functional circuit block prior to the start of operation;

increasing a circuit current of said functional circuit block to a predetermined operation power level before execution of said instruction, in a predetermined time as measured starting from a time of reception of said previous notice signal to shift from a low power consumption mode to an operation mode;

executing an operation of said functional circuit block in said operation mode; and

reducing the circuit current to a predetermined level responsive to completion of execution of said instruction, in a predetermined time as measured after termination of execution of the operation of said functional circuit block to shift to the low power consumption mode.

19. A microprocessor comprising:

at least one functional circuit block, wherein instructions are executed by a selected functional circuit block of said at least one functional circuit block;

a decoder for decoding an instruction and for detecting whether said at least one functional circuit block is decoding said execution of said instruction by a result of decoding said instruction;

an activating circuit for activating said at least one functional circuit block from a low power mode to a normal operation mode when said at least one functional circuit block is required for execution, and deactivating said at least one functional circuit block responsive to completion of execution of said instruction, from said normal operation mode to said low power mode after execution of said instruction.

20. A system having a microprocessor and a memory coupled to said microprocessor through a memory interface of said microprocessor,

wherein said microprocessor comprises;

at least one functional circuit block, wherein an instructions are executed by a selected functional circuit block of said at least one functional circuit block;

a decoder for decoding an instruction and for detecting whether said at least one functional circuit block is required for execution of said instruction by a result of decoding said instruction;

an activating circuit for activating said at least one functional circuit block responsive to said instruction, from a low power mode to a normal operation mode when said at least one functional circuit block is required for execution, and deactivating said at least one functional circuit block responsive to completion of execution of said instruction, from said normal operation mode to said low power mode after execution of said instruction.