Advanced parallel array processor computer package

• US 5,734,921 A
• Filed: 09/30/1996
• Issued: 03/31/1998
• Est. Priority Date: 11/13/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dieffenderfer, James Warren, Dapp, Michael Charles, Miles, Richard Ernest, Smoral, Vincent John, Nier, Richard Edward, Stupp, James Robert
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DAVIS JR, WALTER D
• Application Number:
  US08/723,372
• Time in Patent Office: 547 Days
• Field of Search: 395/800, 395/325, 395/200.01, 364/DIG. 1
• US Class Current: 712/10
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32 K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

Claims

1. A computer package, comprising:

a semiconductor substrate and a housing, a plurality of multi-processor memory elements within said housing on said substrate, said housing configured in a quadflatpack with connections to the housing being provided at all four sides, each substrate containing eight or more processor memory elements, each processor memory element performing a portion of network routing functions, and providing parallel point-to-point connection to adjacent computer packages at each of the four sides of the housing;

wherein said comnputer package provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processor memory elements, each of said processor memory elements having a processor coupled with a dedicated local memory, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.

2. A computer package according to claim 1 wherein said housing is configured to arrange said multi-processor memory elements into various 2 D and 3 D configurations in a package.

3. A computer package according to claim 1 wherein one substrate of eight or more processor memory elements is a first level package module.

4. A computer package according to claim 1 wherein the substrate is the size of a DRAM memory chip.

5. A computer package according to claim 1 wherein the housing connections in four directions are point to point.

6. A computer package according to claim 1 wherein multiple housings connect across 3 or more feet, point-to-point, multi-processor memory element to multi-processor memory element, while maintaining control of the plurality of multi-processor memory elements.

7. A computer package according to claim 1 wherein the computer package broadcasts from multi-processor memory element to multi-processor memory element, with data operations conducted in a multi-processor memory element thereby reducing data path requirements.

8. A computer package according to claim 1 wherein each substrate chip has a broadcast path used as a controller routing tool.

9. A computer package according to claim 1 wherein each substrate has a data stream which connects to a network communication path system.

10. A computer package according to claim 1 wherein the computer package has a power system which is rated in multiples of the number of multi-processor memory elements supported multiplied by about 2.5 or less watts per multi-processor memory element, and wherein power dissipation from a five volt power supply is measured by the number of multi-processor memory elements multiplied by about 2.2 watts per multi-processor memory element.

11. A computer package according to claim 1 wherein the computer package has a thermal design enhanced by the housing to avoid hot spots due to high dissipating components mixed with low dissipating components.

12. A computer package according to claim 1 wherein the computer package has multiple replicated substrates within the housing.

13. A computer package according to claim 1 wherein the computer package is air cooled.

14. A computer package according to claim 1 wherein the computer package has eight substrates in a multiple chip module.

15. A computer package according to claim 1 wherein the computer package houses a plurality of substrates using a multiple chip module.

16. A computer package according to claim 1 wherein each housing with eight or more processor memory elements is arranged in a dip, with pinouts configured as a standard DRAM memory module.

17. A computer package according to claim 1 wherein the computer package has a plurality of copies of a replicated processor which includes a memory with a processor, and part of the memory is assigned to a specific monitoring task, and another part of the memory, with a size programmatically defined, is a massive global memory, addressed point-to-point, with a broadcast to all facility.

18. A computer package according to claim 1 wherein the computer package can be replicated in modules to form a workstation, supercomputer, or controller, or other computer system with the same computer packages.

19. A computer package according to claim 1 wherein the computer package provides an array of memory, CPU and I/O, and functions as processor memory elements of a massively parallel application processor.