Direct-coupled signaling receiver with PL/DPL detector

• US 5,734,975 A
• Filed: 10/24/1996
• Issued: 03/31/1998
• Est. Priority Date: 10/24/1996
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kehler, Walter H., Rollins, Norman T., Zele, Rajesh H.
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): VINCENT, DAVID ROBERT
• Application Number:
  US08/736,180
• Time in Patent Office: 523 Days
• Field of Search: 455/214, 455/312, 455/307, 455/337, 455/338, 455/339, 455/340, 455/308, 455/210, 455/212, 455/221, 455/222, 327/551, 327/552, 327/554
• US Class Current: 455/307
• CPC Class Codes: H04H 20/31 using in-band signals, e.g. subsonic or cue signal

Abstract

A detector circuit (100) for detecting signaling information transmitted with a radio frequency (RF) signal for interpretation by a radio receiver includes a first low pass filter (105) for filtering demodulated audio signals that are directly coupled thereto and for providing a first filtered signal. A second low pass filter (109) is directly coupled with the first low pass filter (105) for filtering the first filtered signal and providing a second filtered signal. A signaling detector (111) is then directly coupled with the second low pass filter (109) for determining the frequency and/or bit code of signaling information included in the second filtered signal.

Claims

1. A detector circuit for selecting signaling information transmitted with a radio frequency (RF) signal for interpretation by a radio receiver comprising:

at least one filter circuit for filtering demodulated audio signals direct current (DC) coupled thereto;

a signaling decoder DC coupled with the at least one filter circuit for determining a frequency and/or bit code of signaling information from the at least one filter circuit; and

wherein the signaling decoder includes a first signaling path and a second signaling path where the first signaling path provides signaling information and direct current (DC) offset information to a switched capacitator subtracting circuit and the second signaling path provides only Dc offset information to the subtracting circuit.

2. A detector circuit as in claim 1 wherein the at least one filter circuit comprises a first active low pass filter and a second active low pass filter having a substantially low gain.

3. A detector circuit as in claim 2 wherein the first active low pass filter is a switched capacitor filter.

4. A detector circuit as in claim 3 wherein the second active low pass filter is a switched capacitor filter.

5. A detector circuit as in claim 1 further wherein the signaling decoder utilizes mixed analog and discrete-time components.

6. A detector circuit as in claim 1 wherein the signaling decoder is comprised of a switched capacitor offset-canceled comparator that is integrated with at least one real resistance.

7. A detector circuit as in claim 1 wherein at least one real resistance is serially segmented and tapped for providing a plurality of signaling time constants.

8. A detector circuit as in claim 1 wherein the signaling decoder is comprised of a switched capacitor offset-canceled comparator and a continuous time low pass filter.

9. A detector circuit as in claim 8 wherein the signaling decoder further includes at least one switch for altering the time constant of the continuous time low pass filter.

10. A detector circuit as in claim 1 wherein information from the first signal path and the second signal path are combined such that a portion of the signal information on the first signal path and the second signal path cancel for providing resultant signaling information to a comparator.

11. A signaling receiver for decoding analog and digital signaling information identifying a specific user among a plurality of users on a radio frequency (RF) channel comprising:

a first low pass switched capacitator filter direct current (DC) coupled to a demodulator for providing an audio signal and DC offset signaling information by a predetermined amount;

a second low pass switched capacitator filter DC coupled to the first low pass switched capacitator filter for filtering the audio signal and providing only the DC offset signaling information;

a detector DC coupled second low pass switched capacitor filter, the detector comprising a continuous time low pass filter and a discrete time comparator for providing a digital representation of the signaling information; and

wherein the detector includes a first signaling path and second signaling path where the first signaling path provides signaling information and direct current (DC) offset information to a switched capacitator subtracting circuit and the second signaling path provides only DC offset information to the subtracting circuit.

12. A signaling receiver as in claim 11 wherein the first low pass switched capacitor filter is an active filter.

13. A signaling receiver as in claim 11 wherein the second low pass switched capacitor filter is an active filter.

14. A signaling receiver as in claim 11 further wherein the signaling receiver utilizes discrete-time and analog components.

15. A signaling receiver as in claim 11 wherein the discrete time comparator is a switched capacitor offset-canceled comparator that is integrated with at least one real resistance.

16. A signaling receiver as in claim 15 wherein the at least one real resistance is serially segmented and tapped for providing a plurality of signaling time constants.

17. A signaling receiver as in claim 11 wherein the detector further includes at least one switch for altering a time constant of the continuous time low pass filter.

18. A signaling receiver as in claim 11 wherein information from the first signal path and the second signal path are combined such that a portion of the signaling information on the first signal path and the second signal path is canceled providing a resultant signaling information to a comparator.

19. A method for providing a digital representation of signaling information received in a radio receiver comprising the steps of:

receiving a demodulated signal including an audio signal, direct current (DC) offset signaling information and extraneous information from a demodulator located within the radio receiver;

DC coupling the demodulated signal from the demodulator to a first filter;

filtering the demodulated signal in the first filter such that the extraneous information is eliminated and the audio signal and DC offset signaling information is amplified;

DC coupling the audio signal and DC offset signaling information directly to a second filter;

filtering the audio signal and DC offset signaling information in the second filter such that the audio signal is eliminated;

DC coupling the DC offset signaling information directly to a detector having a first signaling path and second signaling path where the first signaling path provides signaling information and direct current (DC) offset information to a switched capacitor subtracting circuit and the second signaling path provides only DC offset information to the switched capacitor subtracting circuit;

detecting the DC offset signaling information such that DC offset of the signaling information is cancelled providing a resultant signaling information; and

converting the resultant signaling information into a digital format for interpretation by the radio receiver.

20. A method for providing a digital representation of signaling information as in claim 19 wherein the first filter is a switched capacitor filter.

21. A method for providing a digital representation of signaling information as in claim 20 wherein the second filter is a switched capacitor filter.

22. A method for providing a digital representation of signaling information as in claim 19 wherein the detecting step includes a mixed analog and discrete time circuit.

23. A method for providing a digital representation of signaling information as in claim 19 wherein the detecting step utilizes a switched capacitor offset-canceled comparator that is integrated with at least one real resistance.

24. A method for providing a digital representation of signaling information as in claim 23 wherein the at least one real resistance is serially segmented and tapped for providing a plurality of signaling time constants.

25. A method for providing a digital representation of signaling information as in claim 19 further comprising the step of:

altering a time constant of the detector using at least one switch for changing at least one real resistance.

26. A method for providing a digital representation of signaling information as in claim 25 wherein the at least one real resistance is serially segmented and tapped for providing a plurality of signaling time constants.