Device for detecting failure of microcomputer in antilock controller

• US 5,735,583 A
• Filed: 05/17/1995
• Issued: 04/07/1998
• Est. Priority Date: 09/21/1993
• Status: Expired due to Fees

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Sakaguchi, Masahiro, Katayama, Yoshio, Yasuzumi, Kazumi
• Primary Examiner(s): Graham, Matthew C.
• Application Number:
  US08/436,235
• Time in Patent Office: 1,056 Days
• Field of Search: 303/122.04, 303/122.05, 303/122.06, 303/122.07
• US Class Current: 303/122.05
• CPC Class Codes: B60T 2270/416 Wheel speed sensor failure
• CPC Class Codes: B60T 8/885 using electrical circuitry

Abstract

An anti-lock controller apparatus is constituted of a single microcomputer to reduce production costs and improve safety and reliability. Signals of wheel speed sensors S₁ to S₄ divided into two groups by an input processing circuit and are inputted to the single microcomputer. The single microcomputer executes two-system input/output processing and checks for abnormalities of the input/output signals.

Claims

1. An antilock controller comprising:

wheel speed detecting means for producing wheel speed signals;

means for splitting each of said wheel speed signals into two identical split signals; and

a single control logic operation circuit including;

a single central processing unit;

at least two input terminals through which said split signals are separately inputted in said logic operation circuit;

a first variable storage means for receiving one of said two split signals;

a second variable storage means for receiving the other of said two split signals;

a first processing program defining a means for controlling said central processing unit to process said one of said two split signals to determine a first output;

a second processing program defining a means which is identical to and separate from said first processing program for controlling said central processing unit to process said split signal to determine a second output;

at least two output terminals through which said first and second outputs are separately outputted;

an output determining logic circuit for processing said first and second outputs and determining an output signal for driving solenoid valves, relays and other driven elements; and

an output abnormality detection circuit for determining whether the output signal is normal by comparing and calculating the signals processed by said output determining logic circuit.

2. An antilock controller as claimed in claim 1 wherein one of said split signals is stored in said first variable storage means;

the other of said split signals is stored in said second variable storage means;

the one of said split signals stored in said first variable storage is processed; and

the other of said split signals stored in said second variable storage means is processed.

3. An antilock controller as claimed in claim 2 further comprising an input terminal monitoring circuit comprising an additional input terminal connected only to one of said output terminals, and an input circuit for monitoring a signal inputted into said additional input terminal from said one of the output terminals.

4. An antilock controller as claimed in claim 3 wherein said output abnormality detection circuit judges that said two outputs are normal if the interval between the times when the two outputs are produced is smaller than a predetermined value, and judges that the two outputs are not normal if this time interval is greater than the predetermined value.

5. An antilock controller as claimed in claim 2 wherein said output abnormality detection circuit judges that said two outputs are normal if the interval between the times when the two outputs are produced is smaller than a predetermined value, and judges that the two outputs are not normal if this time interval is greater than the predetermined value.

6. An antilock controller as claimed in claim 1 further comprising an input terminal monitoring circuit comprising an additional input terminal connected only to one of said output terminals, and an input circuit for monitoring a signal inputted into said additional input terminal from said one of the output terminals.

7. An antilock controller as claimed in claim 6 wherein said output abnormality detection circuit judges that said two outputs are normal if the interval between the times when the two outputs are produced is smaller than a predetermined value, and judges that the two outputs are not normal if this time interval is greater than the predetermined value.

8. An antilock controller as claimed in claim 1 wherein said output abnormality detection circuit judges that said two outputs are normal if the interval between the times when the two outputs are produced is smaller than a predetermined value, and judges that the two outputs are not normal if this time interval is greater than the predetermined value.

9. An antilock controller as claimed in claim 1, wherein said single central processing unit is a single one-chip microcomputer.

10. A control logic operation circuit for use in an antilock controller comprising:

a single control logic operation circuit including a single central processing unit, at least one input terminal, a processing program defining a means for controlling said central processing unit to process an input signal inputted through said input terminal to determine an output, a storage means for storing said input signal and said output, and a

first and a second checking program defining a means for separately controlling said central processing unit to perform logic operations separately from each other, compare the results of the logic operations, and produce an abnormality signal if the results are not coincident with each other.

11. A control logic operation circuit for us in an antilock controller as claimed in claim 10 wherein said input terminal comprises at least two input terminals through which two identical signals obtained by splitting a single input signal are separately inputted, wherein said processing program comprises a first processing circuit and a first variable storage circuit for receiving and processing one of said two split signals, and a second processing circuit and a second variable storage circuit for receiving and processing the other of said two split signals, wherein said single central processing unit processes the signals produced by said first and second groups of circuits to produce a first and a second output, and further comprising at least two output terminals through which said first and second outputs are outputted, respectively, wherein the logic operations in said first and second checking programs are performed before carrying out the logic operations in said first and second processing circuits.

12. A control logic operation circuit for use in an antilock controller as claimed in claim 11 wherein all the commands of the central processing unit including commands for setting and resetting flags, judgement sentence commands, and assignment/takeout commands are shared by said checking programs.

13. A control logic operation circuit for use in an antilock controller as claimed in claim 11, wherein one of said first and second checking programs exclusively performs multiplication and subtraction operations on the data stored in one of said variable storage circuits, whereas the other of said first and second checking programs exclusively performs division and addition operations on the data stored in the other of said variable storage circuits, wherein during a normal antilock control operation a solution obtained by said multiplication and subtraction operations is the same as a solution obtained by said division and addition operations.

14. A control logic operation circuit for use in an antilock controller as claimed in claim 10, wherein one of said first and second checking programs exclusively performs multiplication and substraction operations on the data stored in said storage means, whereas the other of said first and second checking programs exclusively performs division and addition operations on the data stored in said storage means, wherein during a normal antilock control operation a solution obtained by said multiplication and subtraction operations is the same as a solution obtained by said division and addition operations.

15. A control logic operation circuit for use in an antilock controller as claimed in claim 10 wherein all the commands of the central processing logic circuit including commands for setting and resetting flags, judgment sentence commands, and assignment/takeout commands are shared by said checking circuits.

16. An antilock controller as claimed in claim 10, wherein said single central processing unit is a single one-chip microcomputer.