Process for fabricating a fully self-aligned soi mosfet
First Claim
1. A process for fabricating a MOSFET device comprising the steps of:
- providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer;
forming first and second isolation regions in the silicon layer defining an active region therebetween;
planarizing the first and second isolation regions and the active region to form a planar surface;
forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region;
forming a recess in the active region;
forming a first gate electrode in the single crystal silicon body;
forming a gate dielectric layer in the recess;
depositing a gate electrode forming material to fill the recess;
planarizing the gate electrode forming material to form a second gate electrode overlying the gate dielectric layer;
forming an opening through the second gate electrode and the insulating layer;
forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode; and
forming source and drain regions in the active region on either side of the second gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer.
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Accused Products
Abstract
A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).
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Citations
12 Claims
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1. A process for fabricating a MOSFET device comprising the steps of:
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providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer; forming first and second isolation regions in the silicon layer defining an active region therebetween; planarizing the first and second isolation regions and the active region to form a planar surface; forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region; forming a recess in the active region; forming a first gate electrode in the single crystal silicon body; forming a gate dielectric layer in the recess; depositing a gate electrode forming material to fill the recess; planarizing the gate electrode forming material to form a second gate electrode overlying the gate dielectric layer; forming an opening through the second gate electrode and the insulating layer; forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode; and forming source and drain regions in the active region on either side of the second gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A process for fabricating a MOSFET device comprising the steps of:
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providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer; forming first and second isolation regions in the silicon layer defining an active region therebetween; planarizing the first and second isolation regions and the active region to form a planar surface; forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region; forming a recess in the active region, the recess having substantially vertical sides; implanting the active region through the opening in the masking layer to form a first gate electrode in the single crystal silicon body; forming a first insulating sidewall spacer adjacent to the substantially vertical sides; forming a gate dielectric layer in the recess; depositing a gate electrode forming material to fill the recess; planarizing the gate electrode forming material to form a second planar surface and to define a second gate electrode overlying the gate dielectric layer; removing the masking layer to expose a wall surface of the gate electrode; forming an opening through the second gate electrode and the insulating layer; forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode; forming a second insulating sidewall spacer adjacent to the wall surface; forming source and drain regions in the active region on either side of the first gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer; and forming refractory-metal silicide regions in the source and drain regions and at an upper surface of the gate electrode. - View Dependent Claims (9, 10, 11, 12)
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Specification