Process for fabricating a fully self-aligned soi mosfet

• US 5,736,435 A
• Filed: 07/03/1995
• Issued: 04/07/1998
• Est. Priority Date: 07/03/1995
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lutze, Jeffrey, Ajuria, Sergio, Poon, Stephen, Venkatesan, Suresh
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/497,317
• Time in Patent Office: 1,009 Days
• Field of Search: 437/21, 437/40 FT, 437/41 RG, 437/41 TFT, 437/203, 437/62, 437/44, 437/45, 437/40 GS, 437/41 GS, 257/347, 257/348, 257/349, 257/350, 257/351, 257/352, 257/353, 257/354, 153/636.1, 430/151, 430/270, 430/282, 430/589
• US Class Current: 438/151
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

Claims

1. A process for fabricating a MOSFET device comprising the steps of:

providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer;

forming first and second isolation regions in the silicon layer defining an active region therebetween;

planarizing the first and second isolation regions and the active region to form a planar surface;

forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region;

forming a recess in the active region;

forming a first gate electrode in the single crystal silicon body;

forming a gate dielectric layer in the recess;

depositing a gate electrode forming material to fill the recess;

planarizing the gate electrode forming material to form a second gate electrode overlying the gate dielectric layer;

forming an opening through the second gate electrode and the insulating layer;

forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode; and

forming source and drain regions in the active region on either side of the second gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer.

2. The process of claim 1, further comprising the steps of:

removing the masking layer to expose a wall surface of the first gate electrode prior the step of forming source and drain regions; and

forming an insulating sidewall spacer adjacent to the wall surface.

3. The process of claim 1, further comprising the step of forming a second gate electrode in the single crystal silicon body, wherein the second gate electrode is separated from the channel region by the insulating layer.

4. The process of claim 3 further comprising the steps of:

forming an opening through the first gate electrode and the insulating layer; and

forming a refractory-metal plug in the opening to electrically couple the first gate electrode to the second gate electrode.

5. The process of claim 1, further comprising the step of forming an insulating sidewall spacer in the recess prior to the step of forming a gate dielectric layer.

6. The process of claim 5, wherein the step of planarizing the gate electrode forming material comprises forming a gate electrode having a top surface and a bottom surface, wherein a lateral dimension of the top surface is greater than a lateral dimension of the bottom surface.

7. The process of claim 1, wherein all of the channel, source, and drain regions lie within the silicon layer.

8. A process for fabricating a MOSFET device comprising the steps of:

providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer;

forming first and second isolation regions in the silicon layer defining an active region therebetween;

planarizing the first and second isolation regions and the active region to form a planar surface;

forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region;

forming a recess in the active region, the recess having substantially vertical sides;

implanting the active region through the opening in the masking layer to form a first gate electrode in the single crystal silicon body;

forming a first insulating sidewall spacer adjacent to the substantially vertical sides;

forming a gate dielectric layer in the recess;

depositing a gate electrode forming material to fill the recess;

planarizing the gate electrode forming material to form a second planar surface and to define a second gate electrode overlying the gate dielectric layer;

removing the masking layer to expose a wall surface of the gate electrode;

forming an opening through the second gate electrode and the insulating layer;

forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode;

forming a second insulating sidewall spacer adjacent to the wall surface;

forming source and drain regions in the active region on either side of the first gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer; and

forming refractory-metal silicide regions in the source and drain regions and at an upper surface of the gate electrode.

9. The process of claim 8, further comprising the step of implanting the active region through the opening in the masking layer to form a second gate electrode in the single crystal silicon body, wherein the second gate electrode is separated from the channel region by the insulating layer.

10. The process of claim 9 further comprising the steps of:

forming an opening through the first gate electrode and the insulating layer; and

forming a refractory-metal plug in the opening to electrically couple the first gate electrode to the second gate electrode.

11. The process of claim 8, wherein the step of depositing a gate electrode forming material comprises depositing a material selected from the group consisting of polycrystalline silicon, a refractory metal, and a refractory metal silicide.

12. The process of claim 8, wherein all of the channel, source, and drain regions lie within the silicon layer.