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Process for fabricating a fully self-aligned soi mosfet

  • US 5,736,435 A
  • Filed: 07/03/1995
  • Issued: 04/07/1998
  • Est. Priority Date: 07/03/1995
  • Status: Expired due to Fees
First Claim
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1. A process for fabricating a MOSFET device comprising the steps of:

  • providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer;

    forming first and second isolation regions in the silicon layer defining an active region therebetween;

    planarizing the first and second isolation regions and the active region to form a planar surface;

    forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region;

    forming a recess in the active region;

    forming a first gate electrode in the single crystal silicon body;

    forming a gate dielectric layer in the recess;

    depositing a gate electrode forming material to fill the recess;

    planarizing the gate electrode forming material to form a second gate electrode overlying the gate dielectric layer;

    forming an opening through the second gate electrode and the insulating layer;

    forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode; and

    forming source and drain regions in the active region on either side of the second gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer.

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