Monolithic continuous-time analog filters
First Claim
Patent Images
1. A monolithic continuous-time analog filter, comprising:
- a plurality of delay cells each having an input for receiving a continuous-time analog input signal, and an output for outputting a continuous-time internal signal, said delay cells each having delay parameters, said delays cells each comprising a continuum of semiconductor material between said cell input and said cell output, said continuum having a series resistance and parallel capacitance with an RC time constant determinative of the delay parameter of said each cell;
a plurality of multiplier circuits each having its input coupled to the output of a delay cell, and having a weight coefficient, said continuous-time internal signals being multiplied by said weight coefficient to produce a plurality of weighted continuous-time internal signals; and
summing means being coupled to said plurality of multiplier circuits for adding the weighted continuous time internal signals to generate a continuous-time output signal at its output, so that the monolithic continuous-time analog filter is responsive to the selected value of delay cell parameters and weight coefficients.
1 Assignment
0 Petitions
Accused Products
Abstract
A continuous-time analog filter receiving a continuous-time analog input signal is provided. The filter utilizes a plurality of delay cells for receiving the input signal, and then processes the input signal through taps having specific weight values. The signal is multiplied by the weight factors and then summed to produce a continuous-time analog output signal.
23 Citations
33 Claims
-
1. A monolithic continuous-time analog filter, comprising:
-
a plurality of delay cells each having an input for receiving a continuous-time analog input signal, and an output for outputting a continuous-time internal signal, said delay cells each having delay parameters, said delays cells each comprising a continuum of semiconductor material between said cell input and said cell output, said continuum having a series resistance and parallel capacitance with an RC time constant determinative of the delay parameter of said each cell; a plurality of multiplier circuits each having its input coupled to the output of a delay cell, and having a weight coefficient, said continuous-time internal signals being multiplied by said weight coefficient to produce a plurality of weighted continuous-time internal signals; and summing means being coupled to said plurality of multiplier circuits for adding the weighted continuous time internal signals to generate a continuous-time output signal at its output, so that the monolithic continuous-time analog filter is responsive to the selected value of delay cell parameters and weight coefficients. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A monolithic continuous-time analog filter, comprising:
-
a body of semiconductor material; and integrated on said body of semiconductor material a plurality of delay cells, a plurality of multiplier circuits and summing means; said plurality of delay cells each having an input for receiving a continuous-time analog input signal, an output for outputting a continuous-time internal signal, and an all-pass Bessel filter connected between said cell input and said cell output, said Bessel filter comprising a network of integrators coupled to each other; said plurality of multiplier circuits each having its input coupled to the output of a delay cell, and having a weight coefficient, said continuous time internal signals being multiplied by said weight coefficient to produce a plurality of weighted continuous-time internal signals; and said summing means being coupled to said plurality of multiplier circuits for adding the weighted continuous time internal signals to generate a continuous-time output signal at its output, so that the monolithic continuous-time analog filter is responsive to the selected value of delay cell parameters and weight coefficients. - View Dependent Claims (20)
-
-
21. An electrically tunable monolithic delay circuit for outputting a plurality of delay signals each delayed in time relative to an input signal, said delay circuit comprising:
-
a body of semiconductor material; a signal input for receiving an input signal; a plurality of delay cells in said body of semiconductor material, each delay cell comprising a cell input coupled to said signal input, a cell output for outputting a delayed signal delayed in time relative to the input signal, and a continuum of series resistance and a continuum of parallel capacitance between said cell input and said cell output, said series resistance and parallel capacitance having a nominal RC time constant providing a nominal delay parameter for each delay cell; and a tuning circuit for electrically tuning the resistance of said continuum of series resistance of each said delay cell for tuning the delay parameter of said each delay cell. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
-
Specification