Metering unit with enhanced DMA transfer

• US 5,737,231 A
• Filed: 05/28/1996
• Issued: 04/07/1998
• Est. Priority Date: 11/30/1993
• Status: Expired due to Fees

• Current Assignee: Square D Company (Schneider Electric SE)
• Original Assignee: Square D Company (Schneider Electric SE)
• Inventors: Pyle, Michael W., Carlson, David C.
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): Kemper, M.
• Application Number:
  US08/653,831
• Time in Patent Office: 679 Days
• Field of Search: 364/483, 364/482, 364/492, 324/76.24, 324/76.15, 324/76.38, 324/76.42, 324/76.58, 324/107, 324/76.12, 324/76.11, 361/78, 361/79, 361/85, 361/86, 361/87, 307/353, 307/510, 307/354, 365/222
• US Class Current: 702/61
• CPC Class Codes: G01R 19/2509 Details concerning sampling, digitizing or waveform capturing
• CPC Class Codes: G01R 19/2513 Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
• CPC Class Codes: G01R 21/133 by using digital technique
• CPC Class Codes: G01R 22/00 Arrangements for measuring time integral of electric power or current, e.g. electricity meters

Abstract

An improved metering unit is described which samples a power-related waveform and simultaneously captures its analog signal parameters for temperature and all phases of voltage and current, providing a more accurate and clearer waveform sample that effectively detects harmonics problems and does not require signal interpolation methods. The improved metering unit comprises signal conditioning circuitry interfacing with the power line for sensing temperature and all desired phases of voltage and current parameters of the waveform. The metering unit further comprises a processor having a timer output. The timer output controls track and hold circuitry and an A/D converter. The timer output places the track and hold circuitry in the hold mode to simultaneously capture temperature and all the desired phases of voltage and current of the waveform, and, at the same time, the timer output triggers the A/D converter to convert the captured analog signal parameters into digital sample values.

Claims

1. A metering unit for monitoring power in a distributed power network, wherein a power-related, multi-phase waveform passes through a power line and zero-crossings of the waveform define its cycles, said metering unit comprising:

signal conditioning circuitry disposed adjacent to the power line, for sensing desired phases of analog voltage and current associated with said waveform;

a processor generating a timer output and including DMA controller circuitry;

track and hold circuitry responsive to said timer output for simultaneously capturing intra-cycle voltage values and intra-cycle current values corresponding to each of said desired phases of said distributed power network;

an analog to digital converter coupled to said track and hold circuitry and responsive to said timer output for producing a plurality of distal samples from said intra-cycle voltage values and said intra-cycle current values, said analog to digital converter including a FIFO buffer storing said digital samples, said analog to digital converter providing a transfer signal to said processor upon the filling of said FIFO buffer for initiating a DMA transfer of said digital samples to a memory, said DMA controller circuitry generating a single source address to said FIFO buffer to transfer a portion of each digital sample from said FIFO buffer to said memory;

DMA enhancement circuitry altering said source address received by said FIFO buffer to transfer a remaining portion of each digital sample from said FIFO buffer to said memory during said DMA transfer while said source address generated by said DMA controller circuitry remains the same; and

means for performing at least one power-related calculation for said distributed power network by directly using said digital samples in said memory.

2. The metering unit of claim 1 wherein said processor includes a frequency determinator to determine a frequency of said waveform, said processor responsive to said frequency determinator and programming said timer output in response to said frequency.

3. The metering unit of claim 1 wherein said timer output has a duty cycle, said A/D converter digitizing said intra-cycle voltage values and said intra-cycle current values within said duty cycle.

4. The metering unit of claim 3 wherein said track and hold circuitry holds said analog voltage and current parameters while said A/D converter digitizes said intra-cycle voltage values and said intra-cycle current values.

5. The metering unit of claim 1 further including non-volatile memory and a power supply providing a power fail signal to said processor upon an impending power loss, wherein said processor includes a non-volatile memory protection feature responsive to said power fail signal which prevents said processor from resetting until said processor completes writing into non-volatile memory.

6. The metering unit of claim 5 wherein said non-volatile memory protection feature includes a critical action flag and a power fail flag, said critical action flag indicating a write to said non-volatile memory, and said power fail flag responsive to said power fail signal.

7. The metering unit of claim 1 wherein said DMA enhancement circuitry toggles said least significant bit of said source address from said DMA controller circuitry while said source address generated by said DMA controller circuitry remains the same to transfer all of said digital samples in said buffer to said memory before said DMA transfer ends.

8. A method for monitoring power in a distributed power network, wherein a power-related, multi-phase waveform passes through a power line and zero-crossings of the waveform define its cycles, said method comprising the steps of:

sensing desired phases of analog voltages and currents associated with said waveform;

generating a timer output;

simultaneously capturing intra-cycle voltage values and intra-cycle current values corresponding to each of said desired phases of said distributed power network;

converting said intra-cycle voltage values and said intra-cycle current values into digital samples in response to said timer output;

storing said digital samples in a FIFO buffer;

providing a transfer signal to a processor upon the filling of the FIFO buffer for initiating a DMA transfer of said digital samples to a memory;

generating a single source address to said FIFO buffer by said processor to transfer a portion of each digital sample from said FIFO buffer to said memory;

altering said source address received by said FIFO buffer by DMA enhancement circuitry to transfer a remaining portion of each digital sample from said FIFO buffer to said memory during said DMA transfer while said address generated by said processor remains the same; and

performing at least one power-related calculation for said distributed power network by directly using said digital samples in said memory.

9. The method of claim 8 further comprising the steps of:

determining the frequency of said waveform; and

programming said timer output in response to said frequency determination.

10. The method of claim 8 further comprising the steps of:

providing said timer output with a duty cycle; and

digitizing said intra-cycle voltage values and said intra-cycle current values within said duty cycle.

11. The method of claim 10 further comprising the step of holding said intra-cycle voltage values and said intra-cycle current values while said A/D converter digitizes said intra-cycle voltage values and said intra-cycle current values.

12. The method of claim 8 further comprising the steps of:

providing a power fail signal to said processor upon an impending power loss; and

responding to said power fail signal when said processor is updating non-volatile memory by preventing said processor from resetting until said processor completes writing into non-volatile memory.

13. The method of claim 12 further comprising the steps of:

setting a critical action flag to indicate a write to said non-volatile memory; and

setting said power fail flag in response to said power fail signal.

14. A metering unit for monitoring power in a distributed power network, wherein a power-related, multi-phase waveform passes through a power line and zero-crossings of the waveform define its cycles, said metering unit comprising:

an analog to digital converter producing digital samples from intra-cycle voltage values and intra-cycle current values and having a buffer, said buffer storing said digital samples;

a memory coupled to said analog to digital converter for storing said digital;

a processor including DMA controller circuitry responsive to a transfer signal from said analog to digital converter upon the filling of said buffer for initiating a DMA transfer of said digital samples from said buffer to said memory, said DMA controller circuitry generating a source address to said buffer to transfer a portion of each digital sample from said buffer to said memory; and

DMA enhancement circuitry altering said source address received by said buffer to transfer a remaining portion of each digital sample from said buffer to said memory during said DMA transfer while said source address generated by said DMA controller circuitry remains the same.

15. The metering unit of claim 14 wherein said DMA enhancement circuitry toggles said least significant bit of said source address from said DMA controller circuitry while said source address generated by said DMA controller circuitry remains the same to transfer all of said digital samples in said buffer to said memory before said DMA transfer ends.

16. A method for monitoring power in a distributed power network, wherein a power-related, multi-phase waveform passes through a power line and zero-crossings of the waveform define its cycles, said method comprising the steps of:

converting intra-cycle voltage values and intra-cycle current values into digital samples;

storing said digital samples in a buffer;

providing a transfer signal to a processor upon the filling of the buffer to initiate a DMA transfer of said digital samples to a memory;

generating an address to said buffer by said processor to transfer a portion of each digital sample from said buffer to said memory; and

altering said address received by said buffer by DMA enhancement circuitry to transfer a remaining portion of each digital sample from said buffer to said memory during said DMA transfer while said address generated by said processor remains the same.