Method and apparatus for verifying stored data

• US 5,737,339 A
• Filed: 12/18/1995
• Issued: 04/07/1998
• Est. Priority Date: 02/08/1994
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Koyanagi, Norio, Goto, Kota
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elmore, Stephen C.
• Application Number:
  US08/573,877
• Time in Patent Office: 841 Days
• Field of Search: 371/21.2, 364/237.85, 235/462, 382/182, 382/183, 396/300
• US Class Current: 714/719
• CPC Class Codes: G06K 17/00 Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
• CPC Class Codes: G06K 7/10 by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation

Abstract

An apparatus for verifying stored data comprises a memory unit, a setting unit, an output unit, and a control unit. The memory unit stores a plurality of addresses and a plurality of data as the stored data so that the data are associated with the addresses respectively. The setting unit sets a plurality of the data to a plurality of the addresses of the memory unit and selects any of the addresses. The output unit outputs general data which is different from the data and verify the contents of the data stored in the memory unit. The control unit reads out the contents of the stored data corresponding to the address selected by the setting unit from the memory unit to the output unit.

Claims

1. An apparatus for verifying stored data without using a dedicating output unit comprising:

memory means for storing a plurality of original data as said stored data at a plurality of addresses;

setting means for setting the plurality of the original data to respectively correspond to the plurality of the addresses in said memory means and for selecting one of the plurality of the addresses;

control means for reading out one of said plurality of original data from said memory means corresponding to said one address selected by said setting means and for determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

output means for outputting general data which indicates an operation status of the apparatus, for receiving each of said plurality of bits of said one original data one-by-one from said control means, and for outputting said value of said one original data to identify said one original data set to said one address selected by said setting means, said output means including one indicating means for indicating said value of said one original data.

2. An apparatus for verifying stored data as claimed in claim 1, wherein said output means comprises a plurality of indicating means arranged in correspondence with said plurality of bits, respectively, for indicating the value of each of said plurality of bits.

3. An apparatus for verifying stored data as claimed in claim 1, wherein said output means comprises audio means for outputting voice indicating the value of said one original data.

4. An apparatus for verifying stored data as claimed in claim 1, wherein said control means outputs various frequency signals corresponding to the value of each of said plurality of bits to said output means, and said output means comprises audio means for identifying said stored data by varying voice frequency corresponding to said various frequency signals.

5. An apparatus for verifying stored data as claimed in claim 1, wherein said output means comprises segment indicating means having a plurality of segments each for indicating a number in decimal, said control means for converting said plurality of bits to said number in decimal and outputting said number to said segment indicating means.

6. An apparatus for verifying stored data as claimed in claim 1, wherein said output means comprises a plurality of output units corresponding to said stored data, respectively, said memory means storing output information indicating each of said plurality of output units so that said stored data correspond to said output information, respectively, said control means reading out said stored data from said memory means and activating said plurality of output units based on said output information corresponding to the read data to identify the value of the read data.

7. A method for verifying stored data comprising the steps of:

a storing step for storing a plurality of original data as said stored data at a plurality of addresses;

a setting step for setting said plurality of said original data to respectively correspond to said plurality of said addresses and selecting one of said plurality of addresses;

a controlling step for reading out one of said plurality of original data corresponding to said one address selected by said setting step and for determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

an outputting step for outputting general data to indicate an operation status of a device, for receiving each of said plurality of bits of said one original data one-by-one from said controlling step, and for outputting said value of said one original data to identify the one original data set to said one address, said outputting step including one indicating step for indicating the value of said one original data.

8. A method for verifying stored data as claimed in claim 7, wherein said outputting step comprises a plurality of indicating steps respectively corresponding to each of said plurality of bits, to indicate said value of each of said plurality of bits.

9. A method for verifying stored data as claimed in claim 7, wherein said outputting step comprises an audio step for outputting voice indicating the value of said original data.

10. A method for verifying stored data as claimed in claim 7, wherein said controlling step outputs various frequency signals corresponding to the value of each of said plurality of bits, and said outputting step comprises an audio step for identifying said stored data by varying voice frequency corresponding to said various frequency signals.

11. A method for verifying stored data as claimed in claim 7, wherein said outputting step comprises a segment indicating step of activating a plurality of segments each for indicating a number in decimal, said controlling step for converting said plurality of bits to said number in decimal and outputting said number to said segment indicating step.

12. A method for verifying stored data as claimed in claim 7, wherein said outputting step comprises a plurality of output steps respectively corresponding to said stored data, said storing step stores output information indicating each of said plurality of output steps so that said stored data respectively correspond to said output information, said controlling step reading out said stored data and activating said plurality of output steps based on said output information corresponding to said data to identify said value of the read data.

13. An apparatus for verifying stored data without using a dedicating output unit comprising:

memory means for storing a plurality of original data as said stored data at a plurality of addresses, said stored data in said memory means including a plurality of bits in binary represented by "0" and "1";

setting means for setting the plurality of the original data to respectively correspond to the plurality of the addresses in said memory means and for selecting one of the plurality of the addresses;

control means for reading out one of said plurality of original data from said memory means corresponding to said one address selected by said setting means and for determining a value of said one original data; and

output means for outputting general data from a bar code reader to indicate an operation status of reading a bar code by the bar code reader and for outputting said value of said one original data determined by said control means to identify said one original data set to said one address selected by said setting means, said output means outputting said value responsive to said "0" and "1" representation of the plurality of bits stored in said memory means, said output means outputting each of the plurality of bits stored in said memory means at predetermined time intervals, said control means setting said predetermined time intervals between adjacent bit data of said plurality of bits output by said output means.

14. An apparatus for verifying stored data as claimed in claim 13, wherein said control means sets predetermined time intervals between adjacent data of said plurality of bits output by said output means.

15. An apparatus for verifying stored data without using a dedicating output unit comprising:

memory means for storing a plurality of original data as said stored data at a plurality of addresses;

setting means for setting the plurality of the original data to respectively correspond to the plurality of the addresses in said memory means and for selecting one of the plurality of the addresses;

control means for reading out one of said plurality of original data from said memory means corresponding to said one address selected by said setting means and for determining a value of said one original data; and

output means for outputting general data which indicates an operation status of the apparatus and for outputting said value of said one original data determined by said control means to identify said one original data set to said one address selected by said setting means, said output means including;

one indicating means for outputting said general data to indicate the operation status of the apparatus and for outputting the value of the one original data; and

audio means for outputting audio to indicate the operation status of the apparatus and to indicate the value of the one original data.

16. An apparatus for verifying stored data without using a dedicating output unit comprising:

memory means for storing a plurality of original data as said stored data at a plurality of addresses;

setting means for setting the plurality of the original data to respectively correspond to the plurality of the addresses in said memory means and for selecting one of the plurality of the addresses;

control means for reading out one of said plurality of original data from said memory means corresponding to said one address selected by said setting means and for determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

output means for outputting general data which indicates an operation status of the apparatus, for receiving each of said plurality of bits of said one original data one-by-one from said control means, and for outputting said value of said one original data to identify said one original data set to said one address selected by said setting means, said output means including first indicating means for indicating one of said plurality of bits which is "1" and second indicating means for indicating one of said plurality of bits which is "0";

said control means including;

data determination means for sequentially determining whether each of said plurality of bits is "0" or "1"; and

output control means for activating one of said first indicating means and said second indicating means for each of said plurality of bits to identify said value responsive to each of said plurality of bits determined by said data determination means, and said output control means, responsive to each of said plurality of bits, turning on one of said first indicating means and said second indicating means for each of said plurality of bits for a predetermined period and then turning off said one indicating means for a brief period.

17. An apparatus for verifying stored data without using a dedicating output unit comprising:

memory means for storing a plurality of original data as said stored data at a plurality of addresses;

setting means for setting the plurality of the original data to respectively correspond to the plurality of the addresses in said memory means and for selecting one of the plurality of the addresses;

control means for reading out one of said plurality of original data from said memory means corresponding to said one address selected by said setting means and for determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

output means for outputting general data which indicates an operation status of the apparatus, for receiving each of said plurality of bits of said one original data one-by-one from said control means, and for outputting said value of said one original data to identify said one original data set to said one address selected by said setting means;

said control means including;

data determination means for sequentially determining whether each of said plurality of bits is "0" or "1"; and

output control means for activating or non-activating said output means to identify said value responsive to each of said plurality of bits determined by said data determination means.

18. An apparatus for verifying stored data without using a dedicating output unit comprising:

memory means for storing a plurality of original data as said stored data at a plurality of addresses;

setting means for setting the plurality of the original data to respectively correspond to the plurality of the addresses in said memory means and for selecting one of the plurality of the addresses;

control means for reading out one of said plurality of original data from said memory means corresponding to said one address selected by said setting means and for determining a value of said one original data; and

output means for outputting general data which indicates an operation status of the apparatus and for outputting said value of said one original data to identify said one original data set to said one address selected by said setting means;

said memory means storing said stored data and a plurality of times to activate said output means so that said stored data are associated with said plurality of times, respectively;

said control means reading out said stored data from said memory means and activating said output means at the plurality of times corresponding to said read stored data to identify the value of said read stored data by said plurality of times.

19. A method for verifying stored data comprising the steps of:

storing a plurality of original data as said stored data at a plurality of addresses;

setting said plurality of said original data to respectively correspond to said plurality of said addresses and selecting one of said plurality of addresses;

reading out one of said plurality of original data corresponding to said one selected address;

determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

outputting general data to indicate an operation status of a device, receiving each of said plurality of bits of said one original data one-by-one, and outputting said value of said one original data to identify said one original data set to said one selected address;

said outputting step including a first indicating step for indicating one of said plurality of bits which is "1" and a second indicating step for indicating one of said plurality of bits which is "0";

said determining step including a data determination step for sequentially determining whether each of said plurality of bits is "0" or "1", and an output controlling step for activating one of said first indicating step and said second indicating step for each of said plurality of bits to identify said value responsive to each of said plurality of bits determined by said data determination step, and responsive to each of said plurality of bits, for turning on one of said first indicating step and said second indicating step for each of said plurality of bits for a predetermined period and then turning off said one indicating step for a brief period.

20. A method for verifying stored data comprising the steps of:

storing a plurality of original data as said stored data at a plurality of addresses;

setting said plurality of said original data to respectively correspond to said plurality of said addresses and selecting one of said plurality of addresses;

reading out one of said plurality of original data corresponding to said one selected address;

determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

outputting general data to indicate an operation status of a device, receiving each of said plurality of bits of said one original data one-by-one, and outputting said value of said one original data to identify said one original data set to said one selected address;

said determining step including a data determination step for sequentially determining whether each of said plurality of bits is "0" or "1", and an output controlling step for activating or non-activating said outputting step to identify said value responsive to each of said plurality of bits determined by said data determination step.

21. A method for verifying stored data comprising the steps of:

storing a plurality of original data as said stored data at a plurality of addresses;

setting said plurality of said original data to respectively correspond to said plurality of said addresses and selecting one of said plurality of addresses;

reading out one of said plurality of original data corresponding to said one selected address;

determining a value of said one original data, said one original data including a plurality of bits in binary represented by "0" and "1"; and

outputting general data to indicate an operation status of a device and outputting said value of said one original data to identify said one original data set to said one selected address;

said storing step further storing a plurality of times to activate said outputting step so that said stored data are associated with said plurality of times, respectively;

said reading step further reading out said stored data and activating said outputting step at the plurality of times corresponding to said read stored data to identify the value of said read stored data by said plurality of times.

22. A bar code reader, comprising:

a memory unit storing a plurality of original data, the original data being setting data associated with functions of the bar code reader, including a plurality of bits, at a plurality of addresses set at the functions, respectively;

a setting unit setting the plurality of original data to respectively correspond to the plurality of the addresses in said memory unit and selecting one of the plurality of addresses;

a control unit reading out one of said plurality of original data from said memory unit corresponding to said one address selected by said setting unit;

a transferring unit transferring said original data read by said control unit to said output unit bit by bit, to output said original data from said output unit; and

an output unit informing an operator whether a bar code has been read and informing the operator of the original data, bit by bit.

23. A bar code reader as claimed in claim 22, wherein said output unit is a light emitting diode indicating each of the plurality of bits in binary represented by "0" and "1".

24. A bar code reader as claimed in claim 22, wherein said output unit is a speaker varying voices responsive to a value of each of said plurality of bits.

25. A bar code reader as claimed in claim 22, wherein said control unit sets predetermined time intervals between adjacent bit data of said plurality of bits output by said output unit.

26. A bar code reader as claimed in claim 25, wherein said control unit sets predetermined time intervals between adjacent data of said plurality of bits output by said output unit.

27. A bar code reader as claimed in claim 26, wherein the time intervals between adjacent bit data and the time intervals between adjacent data are set at different time intervals.